ATA6613 ATMEL Corporation, ATA6613 Datasheet - Page 269

• Manufacturer Part Number: ATA6613
• Description: Ata6613
• Manufacturer: ATMEL Corporation

Figure 6-103. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Figure 6-104. ADC Timing Diagram, Single Conversion
9111C–AUTO–02/08
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures
a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold
takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-
tional CPU clock cycles are used for synchronization logic.
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. For a summary of conversion times (see
270).
1
1
2
MUX and REFS
Update
2
MUX and REFS
Update
12
3
13
Sample & Hold
4
14
5
15
Sample & Hold
16
6
First Conversion
17
7
One Conversion
18
8
19
9
20
10
Conversion
21
Complete
Conversion
11
22
Complete
23
12
24
13
ATA6612/ATA6613
25
Sign and MSB of Result
Sign and MSB of Result
LSB of Result
Next Conversion
1
Next
Conversion
1
LSB of Result
2
2
MUX and REFS
Update
MUX and REFS
Update
Table 6-97 on page
3
3
269