ATA6613 ATMEL Corporation, ATA6613 Datasheet - Page 316

• Manufacturer Part Number: ATA6613
• Description: Ata6613
• Manufacturer: ATMEL Corporation

6.24.8.1
316
ATA6612/ATA6613
Serial Programming Algorithm
Figure 6-126. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATA6612/ATA6613, data is clocked on the rising edge of SCK.
When reading data from the ATA6612/ATA6613, data is clocked on the falling edge of SCK. See
Figure 6-127 on page 318
To program and verify the ATA6612/ATA6613 in the serial programming mode, the following
sequence is recommended (see four byte instruction formats in
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
2. V
XTAL1 pin.
CC
- 0.3V <
MISO
MOSI
SCK
AV
CC
for timing details.
< V
CC
ck
ck
CC
and GND while RESET and SCK are set to “0”. In some sys-
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
+ 0.3V, however,
RESET
GND
XTAL1
(1)
AV
CC
AVCC
VCC
should always be within 1.8V - 5.5V
+2.7V to 5.5V
+2.7V to 5.5V
Table 6-128 on page
ck
ck
>= 12 MHz
>= 12 MHz
(2)
9111C–AUTO–02/08
318):