ATA6613 ATMEL Corporation, ATA6613 Datasheet - Page 92

• Manufacturer Part Number: ATA6613
• Description: Ata6613
• Manufacturer: ATMEL Corporation

92
ATA6612/ATA6613
Figure 6-24. Synchronization when Reading an Externally Applied Pin Value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in
the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
Figure 6-25. Synchronization when Reading a Software Assigned Pin Value
Figure
INSTRUCTIONS
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
SYSTEM CLK
SYNC LATCH
6-25. The out instruction sets the “SYNC LATCH” signal at the positive edge of
PINxn
PINxn
r17
r16
r17
out PORTx, r16
XXX
t
pd, max
0x00
0x00
XXX
nop
t
pd
t
pd, min
0xFF
in r17, PINx
in r17, PINx
0xFF
0xFF
9111C–AUTO–02/08