KSZ8841-16 Micrel Semiconductor, KSZ8841-16 Datasheet - Page 29

• Manufacturer Part Number: KSZ8841-16
• Description: Single-port Ethernet Mac Controller With Non-pci Interface
• Manufacturer: Micrel Semiconductor

Regardless of whether the transfer is synchronous or asynchronous, if the address la
ADSN to latch the incoming signals A[15:1
Note: If the local device decoder is used
indicate that the KSZ8841M is successfully
Asynchronous Interface
For as
synch
throug
There is no data burst support for asynchronous transfer. All asynchronous transfers are single-data transfers. The BIU,
however, provides flexible asynchronous interfacing to communicate with various
major ways of interfacing with the system (
1. Interfacing with the system/host relyin
November 2005
Micrel Confidential
transfer: The typical example for this a
ronous
hout th
Signal
INTR
Synchronous Transfer Signals
VLBUSN
CYCLEN
SWR
SRDYN
RDYRTNN
BCLK
Asynchronous Transfer Signals
RDN
WRN
ARDY
Note 1: I = Input. O = Output. I/O = Bi-direction al.
ynchro
e entire asy chronous transfe
nous trans
dedicated
T
O
I
I
I
O
I
I
I
I
O
fers
n
s
ype
ignals CYCLEN
, the asynchr
(1)
Tab
g on local device decoding and having stable address thro
], AEN, BE3N, BE2N, BE1N, and BE0N.
onous dedicated signals RDN (for read)
, SWR, and RD
host) are.
Function
application). When asserted, the device’s local decoding logic is ignored
and the 32-bit access to QMU Data Register is assumed.
Interrupt
VLBUS
VLBUSN = 0, VLBus-like cycle.
VLBUSN = 1, burst cycle (both host/system and KSZ8841M can insert wait
state)
CYCLEN
For VLBus-like access: used to sample SWR when asserted.
For burst access: used to connect to IOWC# bus signal to indicate burst
write.
Write/Read
F
F
read.
Synchronous Ready
For VLBus
VLBus.
For burst a
during the Data Re
Ready Return
For VLBus-like access: exactly like RDYRTNN signal in VLBus to end the
cycle.
For burst acce
N
K
B
A
A
A
T
pplication is ISA-like bus interface using latched address signals as
in either synchronous or asynchronous transfers, LDEVN will be
r.
le 2
targeted. The signal LDEVN is a com
or VLBus-like access: used to indicate
or burst access: used to connect to IORC# bus signal to indicate burst
SZ8841
his signal is asserted (Low
ote tha
us Clo
sy
sy
sy
nchronous Read
nchronous Write
nchronous Read
. Bus I
t th
ck
M
-like access: exactly the same signal definition of nSRDY in
ccess: insert wait state by KSZ8841M whenever necessary
.
nte
e wait s
29
ss: exactly like EXRDY signal in EISA to insert wait states.
rface U
gister access.
YRTNN are de-asserted and stay at the same logic level
tat
es are in rted by system logic (memory
y
nit
Signa
) to insert wait states.
se
l Gr
ouping
write (High) or read (Low) transfer.
binatorial decode of AEN and A[15:4].
applications and architectures. Three
tch is required, use the rising edge of
or WRN (for write) toggle, but the
KSZ8841-16/32 MQL/MVL
) not by
ughout the whole
asserted to
shown
Rev 1.3