KSZ8841-16 Micrel Semiconductor, KSZ8841-16 Datasheet - Page 61

• Manufacturer Part Number: KSZ8841-16
• Description: Single-port Ethernet Mac Controller With Non-pci Interface
• Manufacturer: Micrel Semiconductor

Bank 17 RX Frame Data Pointer Register (0x06): R
The value of this register determines the address to be accessed within the RXQ frame buffer. When the Auto Increment
is set, it will automatically increment th
T
word access.
Bank 17 QMU Data Register Low
This register QDRL(0x08-0x09) contains the Low data word presently addressed by the pointer register. Reading maps
from the RXQ, and writing maps to the TXQ.
Bank 17 QMU Data Register High
This register QDRH(0x0A-0x0B) co
from the RXQ, and writing maps to
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Bi
15
14
13-11
10-0
Bit
15-0
Bit
15-0
he c
t
ounte
Defa
-
0x0
-
0x000
Default Value
-
De
-
r is increment
fault Value
ult Value
ed
R/W
RO
RW
RO
RW
R/W
RW
R/W
RW
is by ne for every
o
the TXQ.
(0x08): QDRL
ntains the High data word presently addressed by the poin
Description
Reserved.
RXFPAI RX F
When this bit is set, the RXQ Address register increments automatically on access
to the data register. The increment is by one for every byte access, by two for
word access, and by four for every double word access.
When this bit is rese
access the RX frame location.
Reserved.
RXFP RX Fra
RX Frame d
This field reset to next availab
is issued (through the RXQ co
Description
QDRL Queue Data Register Low
This register is mapped into two uni-directional buffers for 16-bit buses, and one uni-
directional buffer for 32-bit buses, (TXQ when Write, RXQ when Read) that allow
moving words to and from the KSZ
odd, or Dword
order. This
for 16-bit bu
operations.
Description
QDRL Queue Data Register High
This register is mapped into two uni-directional buffers for 16-bit
directional buffer for 32-bit buses, (TXQ when Write, RXQ when
moving words to and from the KSZ8841M regardless of whether the pointer is even,
odd, or dword aligned. Byte, word, and Dword ac
order. This register along with DQRL is mapped into two consecutive word locations
for 16-bit buses, or one word location for 32-bit buses, to facilitate Dword move
operations.
(0x0A): QDRH
e RXQ Pointer on read accesses to the data register.
register along with DQRH is mapped into two consecutive word locations
ata pointer index to the Data register for access.
ses, or one word location for 32-bit buses, to facilitate Dword move
byte access, by two for every word access, and by four for every double
rame Pointer Auto Increment
me Pointer
aligned. Byte, word, and Dword access can be mixed on the fly in any
XFDPR
t, the RX frame data pointer is manually controlled by user to
61
le RX frame location when RX Frame release command
mmand register).
8841M regardless of whether the pointer is even,
cess can be mixed on the fly in any
Read) that allow
buses, and one uni-
KSZ8841-16/32 MQL/MVL
ter register. Reading maps
every
es
Rev 1.3