KSZ8841-16 Micrel Semiconductor, KSZ8841-16 Datasheet - Page 63

• Manufacturer Part Number: KSZ8841-16
• Description: Single-port Ethernet Mac Controller With Non-pci Interface
• Manufacturer: Micrel Semiconductor

Bank 18 Receive Status R
This register indicates the status of
in the RXQ.
November 2005
Micrel Confidential
14
13
12
11
10
9
8
7
6-0
Bit
15
14-8
7
6
5
0x0
0x0
0x0
0x0
0x0
0x1
0x1
0x0
-
De
-
-
-
-
-
fault Value
RO
(W1C)
RO
(W1C)
RO
(W1C)
RO
(W1C)
RO
(W1C)
RO
(W1C)
RO
(W1C)
RO
(W1C)
RO
egis
R/W
RO
RO
RO
RO
RO
ter
(0x04): RXSR
the current received frame and mirrors the Receive Status
Description
RXFV Receive
When set, it ind
The status information currently in this location
When clear, it indicates that there is either no pending
current frame is still in the process of receiving.
Reserved.
RXBF Receive Broadcast Frame
When set, it in
RXMF Receive Multicast Frame
When set, it indicates that this frame has a multicast address (including the broadca
address).
RXUF Receive Unicast Frame
This edge-triggered interrupt status is cleared by writing 1 to this bit.
TXIS Transmit
When this bit is set, it indicates that the
the MAC interface and the QMU T
This edge-triggered interrupt status is cleared by
RXIS Receive Interrupt Status
When this bit is set, it indicates that the QMU RXQ has rece
MAC interface and the frame is ready for the host CPU to pr
This edge-triggered interrupt status
TXUIS Transmit Underrun Interrupt Status
When this bit is set, it indicates that the transmit underru
This edge-triggered interrupt statu
RXOIS Receive Overrun Interrupt Status
When this bit is set, it indicates that the Receive Overru
This edge-triggered interrupt status is cleared b
RXEIS Receive Early Receive Interrupt Status
When this bit is set, it indicates that the Early Receive status has o
This edge-triggered interrupt status is cleared
TXPSIE Transmit Process Stopped Status
When this bit is set, it indicates that the Transmit Process has sto
This edge-triggered interrupt status is cleared by w
RXPSIE Receive Process Stopped Status
When this bit is set, it indicates that the Receive Process has
This edge-triggered interrupt status is cleared by writing 1
RXEFIE Receive Error Frame Interrupt Status
When this bit is set, it indicates that the Receive error frame status has occ
This edge-triggered interrupt status is cleared by writing
Reserved.
dicates that this frame has a broadcast address.
icates that the present frame in the receive packet memory is valid.
Frame Valid
Status
63
s is cleared by writing 1 to this bit.
XQ is ready for new frames from the host.
is cleared by writing 1 to this bit.
TXQ MAC has transmitted at least a frame on
by writing 1 to this bit.
is also valid.
y writing 1 to this bit.
writing 1 to this bit.
riting 1 to this bit.
receive frame or that the
n status has occurred.
n condition has occurred.
1 to this bit.
to this bit.
ived a frame from the
ocess.
stopped.
KSZ8841-16/32 MQL/MVL
pped.
word of the Receive Frame
ccurred.
urred.
st
Rev 1.3