MC56F836 Freescale Semiconductor, Inc, MC56F836 Datasheet - Page 123

• Manufacturer Part Number: MC56F836
• Description: 56f8300 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

6.5.8.2
This bit selects the alternate function for GPIOD1.
6.5.8.3
6.5.8.4
This bit selects the alternate function for GPIOC3.
6.5.8.5
This bit selects the alternate function for GPIOC2.
6.5.8.6
This bit selects the alternate function for GPIOC1.
6.5.8.7
This bit selects the alternate function for GPIOC0.
6.5.9
The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power
savings feature. The clocks can be individually controlled for each peripheral on the chip.
Freescale Semiconductor
Preliminary
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0 = CS3
1 = CAN2_RX
0 = CS2
1 = CAN2_TX
0 = HOME1/TB3 (default - see “Switch Matrix Mode” bits of the Quad Decoder DECCR register in the
56F8300 Peripheral User Manual)
1 = SS1
0 = INDEX1/TB2 (default)
1 = MISO1
0 = PHASEB1/TB1 (default)
1 = MOSI1
0 = PHASEA1/TB0 (default)
1 = SCLK1
Peripheral Clock Enable Register (SIM_PCE)
GPIOD1 (D1)—Bit 5
GPIOD0 (D0)—Bit 4
GPIOC3 (C3)—Bit 3
GPIOC2 (C2)—Bit 2
GPIOC1 (C1)—Bit 1
GPIOC0 (C0)—Bit 0
56F8365 Technical Data, Rev. 7
Register Descriptions
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