MC56F836 Freescale Semiconductor, Inc, MC56F836 Datasheet - Page 19

• Manufacturer Part Number: MC56F836
• Description: 56f8300 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Preliminary
CLKMODE
V
OCR_DIS
EXTAL
SSA_ADC
Signal
V
V
V
V
Name
XTAL
V
V
CAP
CAP
CAP
CAP
PP
PP
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued)
1
2
1
2
3
4
Pin No.
122
119
95
71
49
75
13
79
74
73
5
Supply
Supply
Output
Input/
Type
Input
Input
Input
Input
Chip-driven
During
Supply
56F8365 Technical Data, Rev. 7
Reset
State
Input
Input
Input
Input
ADC Analog Ground — This pin supplies an analog ground to
the ADC modules.
On-Chip Regulator Disable —
Tie this pin to V
Tie this pin to V
This pin is intended to be a static DC signal from power-up to
shut down. Do not try to toggle this pin for power savings
during operation.
V
connect each pin to a 2.2μF or greater bypass capacitor in order
to bypass the core logic voltage regulator, required for proper chip
operation. When OCR_DIS is tied to V
these pins become V
regulated 2.5V power supply.
Note: This bypass is required even if the chip is powered
with an external supply.
V
circuit for normal functionality.
Clock Input Mode Selection — This input determines the
function of the XTAL and EXTAL pins.
1 = External clock input on XTAL is used to directly drive the input
clock of the chip. The EXTAL pin should be grounded.
0 = A crystal or ceramic resonator should be connected between
XTAL and EXTAL.
External Crystal Oscillator Input — This input can be
connected to an 8MHz external crystal. Tie this pin low if XTAL is
driven by an external clock source.
Crystal Oscillator Output — This output connects the internal
crystal oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the input and
EXTAL connected to GND.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for
the on-chip PLL.
CAP
PP
1 - 2 — These pins should be left unconnected as an open
1 - 4 — When OCR_DIS is tied to V
SS
DD
to enable the on-chip regulator
to disable the on-chip regulator
DD_CORE
Signal Description
and should be connected to a
DD
SS
(regulator disabled),
(regulator enabled),
Signal Pins
19