MC56F836 Freescale Semiconductor, Inc, MC56F836 Datasheet - Page 93
MC56F836
Manufacturer Part Number
MC56F836
Description
56f8300 16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC56F836.pdf
(172 pages)
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5.6.6.2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
5.6.6.3
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
5.6.6.4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
5.6.6.5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.6.6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
Freescale Semiconductor
Preliminary
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00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
00 = IRQ disabled (default)
01 = IRQ is priority level 0
Quadrature Decoder 1 HOME Signal Transition or Watchdog Timer
Interrupt Priority Level (DEC1_HIRQ IPL)—Bits 13–12
SCI 1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)—Bits 11–10
SCI 1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)—
Bits 9–8
Reserved—Bits 7–6
SCI 1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)—
Bits 5–4
56F8365 Technical Data, Rev. 7
Register Descriptions
93