ST92195C STMicroelectronics, ST92195C Datasheet - Page 143

• Manufacturer Part Number: ST92195C
• Description: 48-96 Kbyte Rom Hcmos Mcu With On-screen Display And Teletext Data Slicer
• Manufacturer: STMicroelectronics

ST92195C/D - SYNC CONTROLLER
SYNC CONTROLLER (Cont’d)
7.5.4.3 Free-Running Monitor Sync Mode
This mode is accessed when the MOD1 bit is set.
In this mode, the chassis HSYNC and VSYNC sig-
nals are not used. They are replaced by the sync
signals which are fully Crystal based (use of the in-
ternal main 4 MHz Clock).
Two free-running monitor modes are available:
when the MOD0 bit is reset the Composite Sync
output (CSO) is generated for a 60Hz format;
when the MOD0 bit is set to “1” the Composite
Figure 85. Even/Odd Field Timings
n
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622
522
310
260
d1
623
523
311
261
624
524
312
262
d2
625
525
313
263
2nd TV Field
314
264
1
1
1st TV Field
d1
315
265
2
2
d1
Sync output (CSO) is generated for a 50Hz format.
For both formats, the TV line period is 64µs.
The Composite Sync alternate function Output
(CSO) can be activated or disabled under control
of the VSEP bit.
In Free-Running Monitor Sync mode, the VPOL
control bit is used to control whether an interlaced
or non-interlaced TV context must be generated.
When the non-interlaced context is programmed,
only the “1st TV Field” configuration is generated.
3
3
316
266
317
267
d2
4
4
d1 = 4.75 µs
318
268
5
5
319
269
6
6
d2 = 2.25 µs
(50 Hz Mode)
(60 Hz Mode)
(50 Hz Mode)
(60 Hz Mode)
VR02092C