ST92195C STMicroelectronics, ST92195C Datasheet - Page 62

• Manufacturer Part Number: ST92195C
• Description: 48-96 Kbyte Rom Hcmos Mcu With On-screen Display And Teletext Data Slicer
• Manufacturer: STMicroelectronics

ST92195C/D - RESET AND CLOCK CONTROL UNIT (RCCU)
4.4 CLOCK CONTROL REGISTERS
MODE REGISTER (MODER)
R235 - Read/Write
Register Group: E (System)
Reset Value: 1110 0000 (E0h)
Bits 7:6 = Bits described in Device Architecture
chapter.
Bit 5 = DIV2: OSCIN Divided by 2 .
This bit controls the divide by 2 circuit which oper-
ates on the OSCIN Clock.
0: No division of OSCIN Clock
1: OSCIN clock is internally divided by 2
Bits 4:2 = PRS[2:0]: Clock Prescaling .
These bits define the prescaler value used to
prescale CPUCLK from INTCLK. When they are
reset, the CPUCLK is not prescaled, and is equal
to INTCLK; in all other cases, the internal clock is
prescaled by the value of these three bits plus one.
Bits 1:0 = Bits described in Device Architecture
chapter.
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7
1
1
DIV2
PRS2
PRS1
PRS0
0
0
0
WAIT CONTROL REGISTER (WCR)
R252 - Read/Write
Register Page: 0
Reset Value: 0111 1111 (7Fh)
Bit 7 = Reserved, read as “0”.
Bit 6 = WDGEN: refer to Timer/Watchdog chapter.
WARNING. Resetting this bit to zero has the effect
of setting the Timer/Watchdog to the Watchdog
mode. Unless this is desired, this must be set to
“1”.
Bits 5:3 = WDM[2:0]: Data Memory Wait Cycles.
These bits contain the number of INTCLK cycles
to be added automatically to external Data memo-
ry accesses. WDM = 0 gives no additional wait cy-
cles. WDM = 7 provides the maximum 7 INTCLK
cycles (reset condition).
Bits 2:0 = WPM[2:0]: Program Memory Wait Cy-
cles.
These bits contain the number of INTCLK cycles
to be added automatically to external Program
memory accesses. WPM = 0 gives no additional
wait cycles, WPM = 7 provides the maximum 7
INTCLK cycles (reset condition).
Note: The number of clock cycles added refers to
INTCLK and NOT to CPUCLK.
WARNING. The reset value of the Wait Control
Register gives the maximum number of Wait cy-
cles for external memory. To get optimum per-
formance from the ST9 when used in single-chip
mode (no external memory) the user should write
the WDM2,1,0 and WPM2,1,0 bits to “0”.
7
0
WDGEN WDM2 WDM1 WDM0 WPM2 WPM1 WPM0
0