ST92195C STMicroelectronics, ST92195C Datasheet - Page 63

• Manufacturer Part Number: ST92195C
• Description: 48-96 Kbyte Rom Hcmos Mcu With On-screen Display And Teletext Data Slicer
• Manufacturer: STMicroelectronics

4.5 RESET CONTROL UNIT REGISTERS
The RCCU consists of two registers. They are
PCONF and SDRATH. Unless otherwise stated,
unused register bits must be kept in their reset val-
ue in order to avoid problems with the device be-
haviour.
PLL CONFIGURATION REGISTER (PCONF)
R251 - Read/Write
Register Page: 55
Reset value: 0000 0111 (07h)
Bit 7= SRESEN. Software Reset Enable .
0: RCCU PLL and CSDU are turned off when a
1: RCCU will reset the microcontroller when a
Bits 6:0= Reserved bits. Leave in their reset state.
SRESEN
HALT instruction is performed.
HALT instruction is performed.
7
0
0
0
0
ST92195C/D - RESET AND CLOCK CONTROL UNIT (RCCU)
1
1
0
1
CLOCK SLOW DOWN UNIT RATIO REGISTER
(SDRATH)
R254 - Read/Write
Register Page: 55
Reset value:
0010 0xxx (2xh) after software reset
0100 0xxx (4xh) after watchdog reset
0000 0000 (00h) after external reset
Bit 7 = Reserved bit. Leave in its reset state.
Bit 6 = WDGRES. Watchdog Reset . WDGRES is
automatically set if the last reset was a watchdog
Reset. This is a read only bit.
Bit 5 = SFTRES. Software Reset . SFTRES is au-
tomatically set if the last reset was a software Re-
set. This is a read only bit.
Bits 4:0 = Reserved bits. Please leave in their re-
set state.
7
0
WDGRE
S
SFTRE
S
0
0
x
x
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0
x