ST92195C STMicroelectronics, ST92195C Datasheet - Page 51

• Manufacturer Part Number: ST92195C
• Description: 48-96 Kbyte Rom Hcmos Mcu With On-screen Display And Teletext Data Slicer
• Manufacturer: STMicroelectronics

3.6 EXTERNAL INTERRUPTS
The standard ST9 core contains 8 external inter-
rupts sources grouped into four pairs.
Table 8. External Interrupt Channel Grouping
Each source has a trigger control bit TEA0,..TED1
(R242,EITR.0,..,7 Page 0) to select triggering on
the rising or falling edge of the external pin. If the
Trigger control bit is set to “1”, the corresponding
pending bit IPA0,..,IPD1 (R243,EIPR.0,..,7 Page
0) is set on the input pin rising edge, if it is cleared,
the pending bit is set on the falling edge of the in-
put pin. Each source can be individually masked
through
IMA0,..,IMD1 (EIMR.7,..,0). See
page
The priority level of the external interrupt sources
can be programmed among the eight priority lev-
els with the control register EIPLR (R245). The pri-
ority level of each pair is software defined using
the bits PRL2, PRL1. For each pair, the even
channel (A0,B0,C0,D0) of the group has the even
priority level and the odd channel (A1,B1,C1,D1)
has the odd (lower) priority level.
Figure 25. Priority Level Examples
n
SOURCE
INT.D0:
INT.D1:
INT.C0: 000=0
INT.C1: 001=1
External Interrupt
53.
101=5
100=4
PRIORITY
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A
the
1
0
corresponding
0
0
1
0
0
Channel
INTD1
INTD0
INTC1
INTC0
INTB1
INTB0
INTA1
INTA0
1
Figure 26 on
SOURCE
control
INT.A0: 010=2
INT.A1: 011=3
INT.B1: 101=5
INT.B0: 100=4
EIPLR
VR000151
PRIORITY
bit
Figure 25 on page 51
levels.
Figure 26 on page 53
ternal interrupt control bits and vectors.
– The source of the interrupt channel INTA0 can
– INTA1: by selecting INTS equal to 0, the stand-
– The source of the interrupt channel INTB0 can
– INTB1: setting AD-INT.0 to 1 selects the ADC or
– Setting bit 2 of the CSYCT to 1 selects EOFVBI
– Setting FSTEN (bit 3 of the CSYCT register) to 1
Interrupt channels INTD0 and INTD1 have an in-
put pin as source. However, the input line may be
multiplexed with an on-chip peripheral I/O or con-
nected to an input pin that performs also another
function.
– Setting the INTS1 bit selects the external inter-
Warning: When using channels shared by both
external interrupts and peripherals, special care
must be taken to configure their control registers
for both peripherals and interrupts.
Table 9. Internal/External Interrupt Source
Channel
be selected between the external pin INT0 (when
IA0S = “1”, the reset value) or the On-chip Timer/
Watchdog peripheral (when IA0S = “0”).
ard Timer is chosen as the interrupt.
be selected between the external pin INT2 (when
(SPEN,BMS)=(0,0)) or the SPI peripheral.
I²C as the interrupt source for channel INTB1.
interrupt as the source for INTC0. Setting this bit
to 0 selects external interrupt on INT4.
selects FLDST interrupt for channel INTC1. Set-
ting this bit to 0 selects external interrupt INT5.
rupt 6 and resetting the INTS1 bit selects the
standard timer interrupt.
INTC0
INTC1
INTD0
INTD1
INTA0
INTA1
INTB0
INTB1
A/D Converter / I²C
Internal Interrupt
Standard Timer 0
Standard Timer 1
Timer/Watchdog
SPI Interrupt
(SYNC inter)
(SYNC inter)
EOFVBI
ST92195C/D - INTERRUPTS
Source
FLDST
none
shows an example of priority
gives an overview of the Ex-
External Interrupt
Source
None
None
INT0
INT2
INT4
INT5
INT6
INT7
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