MBM29LV800TE Fujitsu Microelectronics, Inc., MBM29LV800TE Datasheet - Page 25

• Manufacturer Part Number: MBM29LV800TE
• Description: 8m 1m X 8/512 K X 16 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

24
MBM29LV800TE/BE
DQ
Toggle Bit II
*1 : Performing successive read operations from any address will cause DQ
*2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1”
RY/BY
Ready/Busy
Program
Erase
Erase-Suspend Read
Erase-Suspend Program
(Erase-Suspended Sector) *
This toggle bit II, along with DQ
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
address of the non-erase suspended sector will indicate a logic “1” at the DQ
DQ
Program operation is in progress. The behavior of these two status bits, along with that of DQ
as follows :
For example, DQ
(DQ
DIAGRAM”.
Furthermore, DQ
mode, DQ
MBM29LV800TE/BE provide a RY/BY open-drain output pin as a way to indicate to the host system that Em-
bedded Algorithms are either in progress or has been completed. If output is low, devices are busy with either
a program or erase operation. If output is high, devices are ready to accept any read/write or erase operation.
If MBM29LV800TE/BE are placed in an Erase Suspend mode, RY/BY output will be high.
During programming, RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, RY/BY pin is driven low after the rising edge of the sixth WE pulse. RY/BY pin will indicate a busy
condition during RESET pulse. Refer to “RY/BY Timing Diagram during Program/Erase Operation Timing
Diagram” and “RESET, RY/BY Timing Diagram” in “ TIMING DIAGRAM” for a detailed timing diagram. RY/BY
pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V
2
at the DQ
2
6
2
to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
is different from DQ
toggles while DQ
2
2
toggles if this bit is read from an erasing sector.
Mode
bit. However, successive reads from the erase-suspended sector will cause DQ
2
2
and DQ
can also be used to determine which sector is being erased. When device is in the erase
6
does not.) See also “Hardware Sequence Flags” and “DQ
2
6
1
in that DQ
can be used together to determine if the erase-suspend-read mode is in progress.
6
, can be used to determine whether the devices are in the Embedded Erase
6
toggles only when the standard program or Erase, or Erase Suspend
60/70/90
DQ
DQ
DQ
Toggle Bit Status
0
1
7
7
7
2
to toggle during the Embedded Erase Algorithm. If the
Toggle *
Toggle
Toggle
DQ
1
6
6
to toggle.
1
2
bit.
2
vs. DQ
2
to toggle.
7
6
Toggle
Toggle
, is summarized
” in “
DQ
1 *
1
2
2
TIMING
CC
.