MBM29LV800TE Fujitsu Microelectronics, Inc., MBM29LV800TE Datasheet - Page 37

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MBM29LV800TE

Manufacturer Part Number
MBM29LV800TE
Description
8m 1m X 8/512 K X 16 Bit
Manufacturer
Fujitsu Microelectronics, Inc.
Datasheet

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36
MBM29LV800TE/BE
Notes :
PD is the data to be programmed at word address.
DQ
D
Figure indicates the last two bus cycles out of four bus cycles sequence.
These waveforms are for the
PA is the address of the memory location to be programmed.
OUT
7
is the output of the complement of the data written to the device.
Address
Data
WE
OE
CE
is the output of the data written to the device.
Alternate CE Controlled Program Operation Timing Diagram
t
GHEL
t
WS
3rd Bus Cycle
555h
t
WC
t
t
A0h
DS
CP
60/70/90
t
16 mode (the addresses differ from
CPH
t
AS
t
t
WH
DH
PA
t
PD
AH
t
Data Polling
WHWH1
DQ
PA
7
D
OUT
8 mode) .

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