MBM29LV800TE Fujitsu Microelectronics, Inc., MBM29LV800TE Datasheet - Page 26

• Manufacturer Part Number: MBM29LV800TE
• Description: 8m 1m X 8/512 K X 16 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

Byte/Word Configuration
Data Protection
Low V
Write Pulse “Glitch” Protection
Logical Inhibit
Power-Up Write Inhibit
BYTE pin selects byte (8-bit) mode or word (16-bit) mode for MBM29LV800TE/BE devices. When this pin is
driven high, devices operate in word (16-bit) mode. Data is read and programmed at DQ
pin is driven low, devices operates in byte (8-bit) mode. Under this mode, the DQ
address bit, and DQ
and hence commands are written at DQ
for Word Mode Configuration”, “Timing Diagram for Byte Mode Configuration” and “BYTE Timing Diagram for
Write Operations” in “ TIMING DIAGRAM” for the timing diagram.
MBM29LV800TE/BE are designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up, devices automatically
reset internal state machine in Read mode. Also, with its control register architecture, alteration of memory
contents only occurs after successful completion of specific multi-bus cycle command sequences.
Devices also incorporate several features to prevent inadvertent write cycles resulting form V
power-down transitions or system noise.
To avoid initiation of a write cycle during V
than V
disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
the V
to prevent unintentional writes when V
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used.
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Writing is inhibited by holding any one of OE
must be a logical zero while OE is a logical one.
Power-up of the devices with WE
The internal state machine is automatically reset to the read mode on power-up.
CC
CC
Write Inhibit
LKO
level is greater than V
(Min) . If V
14
CC
to DQ
< V
LKO
8
LKO
bits are tri-stated. However, the command bus cycle is always an 8-bit operation
, the command register is disabled and all internal program/erase circuits are
. It is the users responsibility to ensure that the control pins are logically correct
CE
CC
7
is above V
V
CC
to DQ
IL
and OE
power-up and power-down, a write cycle is locked out for V
V
0
IL
and DQ
, CE
LKO
V
(Min) .
MBM29LV800TE/BE
IH
V
15
will not accept commands on the rising edge of WE.
IH
to DQ
, or WE
8
bits are ignored. Refer to “Timing Diagram
V
IH
. To initiate a write cycle, CE and WE
15
/A-
1
pin becomes the lowest
15
to DQ
CC
power-up and
0
. When this
60/70/90
CC
less
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