MBM29DL32XTE Fujitsu Microelectronics, Inc., MBM29DL32XTE Datasheet - Page 44

• Manufacturer Part Number: MBM29DL32XTE
• Description: Flash Memory 32m 4m X 8/2m X 16 Bit Dual Operation
• Manufacturer: Fujitsu Microelectronics, Inc.

44
MBM29DL32XTE/BE
*: Successive reads from the erasing or erase-suspend sector will cause DQ
Notes :1.DQ
Data Polling
In Progress
Exceeded
Time Limits
suspend sector address will indicate logic “1” at the DQ
• DQ
The MBM29DL32XTE/BE devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the
devices will produce the complement of the data last written to DQ
Algorithm, an attempt to read the device will produce the true data last written to DQ
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ
for Data Polling (DQ
For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse
sequence.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid.
If a program address falls within a protected sector, Data Polling on DQ
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for
erasing are protected, Data Polling on DQ
Once the Embedded Algorithm operation is close to being completed, the MBM29DL32XTE/BE data pins (DQ
may change asynchronously while the output enable (OE) is asserted low. This means that the devices are
driving status information on DQ
Depending on when the system samples the DQ
has completed the Embedded Algorithm operation and DQ
may be still invalid. The valid data on DQ
2.DQ
7
4
0
and DQ
is Fujitsu internal use only.
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Suspended
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Suspended
Mode
1
are reserve pins for future use.
7
) is shown in Figure 24.
Erase Suspend Read
(Erase Suspended Sector)
Erase Suspend Read
(Non-Erase Suspended Sector)
Erase Suspend Program
(Non-Erase Suspended Sector)
Erase Suspend Program
(Non-Erase Suspended Sector)
Status
7
at one instant of time and then that byte’s valid data at the next instant of time.
Table 14 Hardware Sequence Flags
-80/90/12
7
0
is active for approximately 400 s, then the bank returns to read mode.
to DQ
7
7
will be read on the successive read attempts.
output, it may read the status or valid data. Even if the device
2
bit.
7
has a valid data, the data outputs on DQ
7
. Upon completion of the Embedded Program
7
Data
DQ
DQ
DQ
DQ
DQ
is active for approximately 1 s, then
2
0
1
0
to toggle. Reading from non-erase
7
7
7
7
7
7
output. Upon completion of the
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
Data
DQ
1
6
7
. During the Embedded
7
Data Data
DQ
output. The flowchart
0
0
0
0
1
1
1
5
DQ
0
1
0
0
0
1
0
3
Toggle*
Toggle
0
Data
DQ
to DQ
N/A
N/A
1*
1
1
2
7
)
6