CS2461 Amphion, CS2461 Datasheet - Page 6

• Manufacturer Part Number: CS2461
• Description: User-programmable Fft/ifft 64-point Block Based
• Manufacturer: Amphion

Figure 5: 7*64 Cycle I/O and Transform Timing
It is noted that the core waits for YEnab being asserted with
the assertion of signal Done to start the downloading process,
to allow the user to control the transform data flow. The
system clock rate is not restricted to the 7*64 cycles and can be
any rate higher than 7X the data rate. In this case if the
downloading result has been completed but loading the next
block is not started, signal Done will be re-asserted to indicate
that the transform result in the internal memory is still
available and can be downloaded again. This feature can be
utilized in C-OFDM modulation systems to perform the guard
interval insertion.
Figure 6 shows the operating flowchart for the CS2461 core.
Figure 6: CS2461 Operating Flowchart
6
CS2461
core for FFT/IFFT transform
Assert CLR to program the
Assert YEnab to download
Assert XBS for one cycle
the transform result from
to load the N-point data
type and scaling factor
block into the core
Done = 1 ?
the core
Output
XRE,XIM
YRE,YIM
YEnab
Done
Busy
YBS
YAV
CLK
XBS
XBIP
CLR
Yes
64-Point Block Based FFT/IFFT
No
0
1
enable_in= 1 ?
Yes
2
No
433 cycles
N -1
448 cycles
The CS2461 keeps track of the numeric values during the
transform computation. If overflow occurs, due to the
insufficient number of shifting down bits programmed for the
given input data, the overflow value is saturated and the
overflow flag signal (YOV) is asserted to alert the application
system. The overflow signal is flagged on-the-fly when the
computation is in progress and is automatically reset when a
new transform is started. It should be noted that as there is an
overlap between the third computation pass and the
downloading transform result in the 7*N cycle operating
mode. An overflow occurring on the last few computations
may not be indicated until the computation has been
completed which is very unlikely to happen in practical
applications.
The processing time, defined from when the last data of a data
block is loaded into the core to when the transform has been
completed, is a function of the transform size. It is equivalent
to the time interval from when output signal Busy is asserted
to when it is de-asserted and is measured in number of clock
cycles listed. The real transform time depends on the clock
frequency.
The transform period includes the transform time and the
data I/O time. It indicates the number of clock cycles required
for the core to perform one transform with input data loading
and transform result downloading. The minimum transform
period is obtained by asserting input signal YEnab as soon as
the output signal Done is asserted and by starting the next
data block as soon as output signal Busy is de-asserted.
PROCESSING TIME AND LATENCY
OVERFLOW HANDLING
0
1
0
1