CS6310 Amphion, CS6310 Datasheet - Page 2

• Manufacturer Part Number: CS6310
• Description: Forward DCT (Encoder)
• Manufacturer: Amphion

PIN/PORT DESCRIPTION
Table 1 describes the input and output ports (shown
graphically in Figure 2) for the CS6310 High Performance
DCT core. Unless otherwise stated, all signals are active high
and bit (0) is the least significant bit.
2
CS6310
CLK
CLR
RSTn
PixStrb
PixIn [7:0]
Q [10:0]
DctDcOut
PixRdy
Signal
High Performance DCT
Input
Input
Input
Input
Input
Output
Output
Output
I/O
Clock signal
Synchronous reset signal
Active low, asynchronous reset signal
Signal to indicate to the core that the first sample in a 8x8 block is available for pro-
cessing. Active high asserted pulse for one CLK period. PixStrb can be left high
after first assertion for continuous processing of data blocks. However, in case of
any gaps between successive blocks, it must be asserted along with first data sam-
ple of a block. Re-assertion of PixStrb within a 8x8 block segment has no effect on
processing.
8-bit wide pixel data input port. The data is burst in on block by block basis. The 8-
bit data for DCT computation is internally level shifted. If the data sequence is cor-
rupted for any reason, the port will continue to read 64 elements of an 8x8 block and
then wait for the assertion of PixStrb to read next valid data block.
11-bit wide DCT coefficient output port. The data is burst out on block by block basis
in column-major order.
DC flag of Q, associated with the first coefficient (DC coefficient) of an 8x8 block,
can also be regarded as the start signal of the block. Active high pulse for one CLK
period.
Active high signal indicates that the core can read a new block of pixel. It goes to a
low state whenever PixStrb has been asserted.
Table 1: I/O Signal Descriptions
Figure 2: CS6310 Core Symbol
CLK
CLR
RSTn
PixStrb
PixIn [7:0]
Description
CS6310
Q [10:0]
PixRdy
DctDcOut