CS6310 Amphion, CS6310 Datasheet - Page 3

• Manufacturer Part Number: CS6310
• Description: Forward DCT (Encoder)
• Manufacturer: Amphion

FUNCTIONAL DESCRIPTION
The DCT is a transform that converts a signal into its
constituent frequency components as represented by a set of
coefficients. For an image, this transform is performed on a 2
dimensional array of samples, resulting in a 2 dimensional
array of coefficients. The data input into the core and output
from the core takes place as a block of 8x8 samples.
The transform can be performed as a one or two stage process.
The two-stage process performs the transform as two separate
one-dimensional transforms. This results in a set of
intermediate results being produced which require storage
and further processing.
The CS6310 performs its function as two 1-dimensional
transforms, using row-column decomposition, with the
intermediate results being stored in the transpose memory.
Figure 3 is a block diagram of the core, showing the main
interfaces and functional blocks.
Figure 3: DCT Block Diagram
The core is initialized on power-up by an asynchronous active
low pulse at the RSTn port or a synchronous active high pulse
at CLR port. Data is burst into the core in blocks of 64, with the
first data value being accompanied by PixStrb signal. The core
accepts 8-bit input signal and produces an 11-bit DCT output.
The blocks shown in the schematic are detailed in the
following sections.
This processing stage comprises a multiplier-accumulator unit
as well as a Cosine lookup table for respective DCT
computations. The input to this stage is the data PixIn from
the I/O port. The output from this processing stage is rounded
to 15-bits to provide the desired computational accuracy and
passed onto the transpose memory.
CS6310
PixStrb
PixIn
CLK
CLR
RSTn
Stage 1
STAGE 1
Transpose
Memory
Stage 2
Dct
PixRdy
DctDcOut
This processing stage comprises a multiplier-accumulator unit
as well as a Cosine lookup tables for respective DCT
computations. The input to this stage is the data stored in the
Transpose Memory by stage 1. This stage, similar to stage1,
performs a 1-D DCT and provides the final 11-bit output at
DCT port.
This 64x15 dual-port RAM stores intermediate results after
first stage of processing. The data is written into the memory
in a row-major order and read from it in a column-major
order, which is effectively a transposition. Along with the
transposition of data, it provides input to the processing stage
for the second stage of DCT processing.
ALGORITHM
The core implements the 2-D DCT as two one-dimensional
operations as defined by the following equation. The results
from the first stage are stored in the transpose memory.
where
The Amphion implementation performs the transform in two
stages with the first stage results being stored in the Transpose
memory. The width of this memory, 15-bit, controls the
number of fractional bits stored and hence influences the
accuracy of the final result. The other factor that controls the
accuracy is the number of fractional bits used when
calculating the cosine coefficients which is 14-bit.
The processing may begin by supplying 8x8 blocks of
unsigned binary samples to the PixIn port, with the first
sample of the block being coincident with the PixStrb.
On entering the core, the 8-bit data is level shifted. The DCT is
performed as two one dimensional DCTs, with the
intermediate results being stored in the transpose memory. In
this high performance DCT, two processing blocks comprising
multipliers and accumulators are used for both the one
S u ( )
C u ( )
C u ( )
s x ( ) = 1-D sample value
S u ( ) = 1-D DCT coefficient
=
C u ( )
----------- -
=
=
2
------ -
1
1
x
TRANSPOSE MEMORY
∑
2
=
7
0
s x ( )
DCT OPERATION
for u=0
for u>0
cos
ACCURACY
STAGE 2
(
-------------------------- -
2x
+
16
1
)uπ
3
TM