CS6652 Amphion, CS6652 Datasheet - Page 5

• Manufacturer Part Number: CS6652
• Description: 2-stream Video Decoder
• Manufacturer: Amphion

Host Interface
H_DataIn
H_DataOut
H_notDatDrv
H_Addr
H_notRegCS
H_notWrite
H_notIRQ
H_ByteEnable
H_notMemRead
H_notMemWrite
H_MemBusy
H_MemRdValid
H_MemRdStrb
H_MemWrValid
H_MemWrReady
Signal
Width
32
32
22
1
1
1
1
4
1
1
1
1
1
1
1
Table 2: CS6652/54 Interface Signal Definitions
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Host Data Input, host write data into the core.
Host Data Output, host read data from the core. This pipelined output reflects the value
of the register selected by H_Addr.
Host Data Drive, indicates that a read is active. This can be used to control external
tristate drivers if required. Active LOW.
Host Address, used to select a register for read/write, or a frame store SDRAM word to
be accessed.
Host Chip Select, active LOW enable signal controls all host register accesses.
Host Write Select, indicates that when H_notRegCS is asserted, the register addressed
by H_Addr will have the value on H_DataIn assigned to it on the rising edge of the Clk
signal, if the appropriate byte write enable signal is also asserted. If it is de-asserted
when H_notRegCS is asserted then a register read is initiated and H_DataOut will
show the selected register’s data on the next tick.
Host Interrupt Request, active LOW output asserted when an interrupt condition is
present and enabled.
Host Byte Write Enables, used on write accesses to control which bytes in a register or
SDRAM word actually get written.
Host memory Read Access, initiates an SDRAM host read transaction.
Host Memory Write Access, initiates an SDRAM host write transaction.
Host Memory Interface Busy, indicates that a memory access transaction is in
progress. This can be used to insert read wait states and to stall for posted writes to
complete.
Host Memory Read Data Valid, indicates that the read data is available on the
H_DataOut port.
Host Memory Read Data Strobe, indicates that the host will consume the data from the
H_DataOut port on the next positive edge of Clk.
Host Memory Write Data Valid, indicates that the host has placed valid write data on the
H_DataIn port. Note that H_ByteEnable should be valid at the same time as the data.
Host Memory Write Data Ready, indicates that the core is ready to consume the data
on H_DataIn on the positive edge of Clk when it is signalled as valid with
H_MemWrValid.
Description
5
TM