CS6652 Amphion, CS6652 Datasheet - Page 7

• Manufacturer Part Number: CS6652
• Description: 2-stream Video Decoder
• Manufacturer: Amphion

Elementary Stream Interface
This interface accepts elementary stream data through the
byte wide ES_Data port. If the core temporarily cannot receive
any further data, or is switching from one elementary stream
to another ES_Stall is asserted. In the CS6652 or CS6654 the
ES_Select output is either a single or 2-bit signal, respectively,
representing the number of the elementary stream that the
core is currently accepting and decoding via ES_Data. This
signal may be used to drive a multiplexer to switch the correct
elementary stream into the core when selected.
Video Stream Parser
VLC Decoder
The VLC Decoder block decodes the Huffman-style variable
length encoded picture data. At the macroblock layer the
outputs of VLC Decoder include:
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The registers used to store stream parameters are replicated as
necessary for each multistream pipeline in the core.
Run-Level Decoding and Inverse Quantization
The output run-level information from the VLC decoder is
converted into complete blocks of 64 quantized DCT
coefficients by the Run-Level Decoder. These DCT coefficients
are encoded in Zigzag or Alternate Scan order and are
converted to natural row order using the Convert Scan (CS)
memory
matrices can be used in the encoding of MPEG video. These
are sent as part of the header information in the stream and
are stored in the Quantization Matrix (QM) memory. The
dequantized DCT blocks are then passed to the Inverse DCT
unit.
Inverse DCT
This high performance unit performs the inverse transform of
the 8x8 DCT Y, Cr and Cb sample blocks. It is capable of
streaming data through continuously transforming an entire
block of 8x8 DCT coefficients into an 8x8 block of (IDCT)
samples or sample prediction error corrections in every 64
clock cycles.
STREAMDECODE: FROM STREAM
DCT block run-level information
Decoded motion vectors for motion compensation
A number of information fields describing the section of
the picture currently being decoded.
DECODING TO INVERSE DCT
before
dequantization.
Custom
quantization
Motion Compensation Unit
For each macroblock in a P- or B-picture the motion
compensation unit takes the decoded motion vectors from the
VLC Decoder and translates them into row and column co-
ordinates for the prediction samples in the reference picture.
The pixels at those co-ordinates are then requested from the
Memory System frame store interface. When the requested
samples are received they are combined with other (forward/
backward/dual prime) samples for the same block to complete
the prediction for the macroblock.
Picture Reconstruction
In this block the final motion compensation prediction
samples are merged with the sample prediction error
corrections from the Inverse DCT unit to form the final
reconstructed samples for the macroblock. They are then
stored in the pixel write-back buffer before being written to
the frame store. In the case of intra macroblocks there are no
prediction samples to add and the output IDCT samples are
written back to the frame store without any further
processing.
There is one StreamControl block for each input elementary
stream. This block is responsible for controlling the decoding
process, reordering, and queuing of pictures for display, for its
designated elementary stream. This task involves the tracking
of the contents of the frame store. For multistream operation
the SDRAM is divided into 2 or 4 separate frame stores in the
CS6652 and CS6654, respectively. The StreamControl block
keeps track of frame buffers and off loads them for reuse once
the frames they contain are no longer required for either
reference or display.
The Frame Store is implemented using two SDRAM chips,
which are commodity PC133 64Mbit parts, each with 2Mx32
organization. The memory interface runs at 133 MHz and can
be directly connected to the SDRAM chips using suitable
pads. MemSys handles the mapping of pixel read and write
requests for motion compensation, reconstructed pixel write-
back, and display into linear memory addresses. Additionally,
the host interface can access the memory banks. Arbitration
between the various accessing units and memory transaction
queues are all maintained by this module.
PICRECON: MOTION COMPENSATION
STREAMCONTROL: FRAME BUFFER
TRACKING AND DISPLAY CONTROL
AND PICTURE RECONSTRUCTION
MEMSYS: SDRAM FRAME STORE
INTERFACE
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