S3055 AMCC (Applied Micro Circuits Corp), S3055 Datasheet - Page 5

• Manufacturer Part Number: S3055
• Description: Sonet/sdh/atm OC-48 16 Bit Transceiver With CDR
• Manufacturer: AMCC (Applied Micro Circuits Corp)

Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 2 is
comprised of a FIFO and a parallel-to-serial register.
The FIFO input latches the data from the PINP/N[15:0]
bus on the rising edge of PICLK. The parallel-to-serial
register is a loadable shift register which takes its paral-
lel input from the FIFO output.
An internally generated divide-by-16 clock, which is
phase aligned to the transmit serial clock as de-
scribed in the Timing Generator description, activates
the parallel data transfer between registers. The serial
data is shifted out of the parallel-to-serial register at
the TSCLK rate.
FIFO
A FIFO is added to decouple the internal and exter-
nal (PICLK) clocks. The internally generated divide-
by-16 clock is used to clock out data from the FIFO.
Phase Initialization (PHINIT) and Lock Detect
(LOCKDET) are used to center or reset the FIFO.
The PHINIT and LOCKDET signals will center the
FIFO after the third PICLK pulse. This is in order to
insure that PICLK is stable. This scheme allows the
user to have an infinite PCLK to PICLK delay
through the ASIC. Once the FIFO is centered, the
PCLK to PICLK delay can have a maximum drift as
specified by Table 17.
FIFO Initialization
The FIFO can be initialized in one of the following
three ways:
1. During power up, once the PLL has locked to the
2. When RSTB goes active, the entire chip is reset.
3. The user can also initialize the FIFO by raising
During normal operation, the incoming data is
passed from the PICLK timing domain to the inter-
nally generated divide-by-16 clock domain. Although
the frequency of PICLK and the internally generated
January 31, 2002 / Revision D
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
reference clock provided on the REFCLK pins,
the LOCKDET will go active and initialize the
FIFO.
This causes the PLL to go out of lock and thus
the LOCKDET goes inactive. When the PLL reac-
quires the lock, the LOCKDET goes active and
initializes the FIFO. Note: PCLK is held in reset
when RSTB is active.
PHINIT.
clock are the same, their phase relationship is arbi-
trary. To prevent errors caused by short setup or
hold times between the two timing domains, the tim-
ing generator circuitry monitors the phase
relationship between PICLK and the internally gener-
ated clock. When a potential setup or hold time
violation is detected, the phase error becomes ac-
tive. When Phase Error (PHERR) conditions occur,
PHINIT should be activated to recenter the FIFO (at
least 2 PCLK periods). This can be done by connect-
ing PHERR to PHINIT. When realignment occurs, up
to ten bytes of data will be lost. The user can also
take in the PHERR signal, process it and send an
output to PHINIT in such a way that idle bytes are
lost during the realignment process. PHERR will go
inactive when the realignment is complete.
RECEIVER OPERATION
The S3055 transceiver chip provides the first stage
of the digital processing of a receive SONET STS-48
bit-serial stream. It converts the bit-serial 2.488 Gbps
data stream into a 16-bit parallel data format. A
loopback mode is provided for diagnostic loopback
(transmitter to receiver). A line loopback (receiver to
transmitter) is also provided.
Clock Recovery
The S3055 clock recovery device performs the clock
recovery function for SONET OC-48 serial data links.
The chip extracts the clock from the serial data inputs
and provides retimed clock and data outputs. A 155.52
MHz reference clock is used for phase locked loop start
up and proper operation under loss of signal conditions.
An integral prescaler and phase locked loop circuit is
used to multiply this reference to the nominal bit rate.
The clock recovery generates a clock that is at the
same frequency as the incoming data bit rate at the
serial data input. The clock is phase aligned by a
PLL so that it samples the data in the center of the
data eye pattern.
The phase relationship between the edge transi-
tions of the data and those of the generated clock
are compared by a phase/frequency discriminator.
Output pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of
the Voltage Controlled Oscillator (VCO), which
generates the recovered clock.
S3055
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