S3055 AMCC (Applied Micro Circuits Corp), S3055 Datasheet - Page 6

• Manufacturer Part Number: S3055
• Description: Sonet/sdh/atm OC-48 16 Bit Transceiver With CDR
• Manufacturer: AMCC (Applied Micro Circuits Corp)

Frequency stability without incoming data is guaran-
teed by an alternate reference input (REFCLK) that
the PLL locks onto when data is lost. If the frequency
of the incoming signal varies by a value greater than
that stated in Table 7, with respect to REFCLKP/N,
the PLL will be declared out of lock, and the PLL will
lock to the reference clock. The assertion of LVTTL
Signal Detect (SDLVTTL) or LVPECL Signal Detect
(SDLVPECL) will also cause an out of lock condition.
The loop filter transfer function is optimized to en-
able the PLL to track the jitter, yet tolerate the
minimum transition density expected in a received
SONET data signal.
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which exceeds the minimum
tolerance proposed for SONET equipment by the
Bellcore TA-NWT-000253 standard, shown in Figure 3.
Lock Detect
The S3055 contains a lock detect circuit which moni-
tors the integrity of the serial data inputs. If the
received serial data fails the frequency test, the PLL
will be forced to lock to the local reference clock.
This will maintain the correct frequency of the recov-
ered clock output under loss of signal or loss of lock
conditions. If the recovered clock frequency deviates
from the local reference clock frequency by a value
greater than that stated in Table 7, the PLL will be
declared out of lock. The lock detect circuit will poll
the input data stream in an attempt to reacquire lock
to data. If the recovered clock frequency is deter-
mined to be within the values stated in Table 7, the
PLL will be declared in lock and the lock detect output
will go active. When SDLVTTL XOR SDLVPECL = 0,
it causes an out of lock condition.
Serial-to-Parallel Converter
The serial-to-parallel converter consists of two 16-bit
registers. The first is a serial-in, parallel-out shift reg-
ister, which performs the serial-to-parallel conversion
clocked by the clock recovery block. On the falling
edge of the Parallel Output Clock (POCLK), the data
in the parallel register is transferred to an output
parallel register which drives POUTP/N[15:0].
6
S3055
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input
is active, a loopback from the transmitter to the re-
ceiver at the serial data rate can be set up for
diagnostic purposes. The differential serial output
data from the transmitter is routed to the serial-to-
parallel block in place of the Receiver Serial Data
(RSD). Transmit Serial Data/Transmit Serial Clock
(TSD/TSCLK) outputs are active. DLEB takes prece-
dence over SDLVPECL and SDLVTTL.
Line Loopback
The line loopback circuitry selects the source of the
data and clock which is output on TSD and TSCLK.
When the Line Loopback Enable (LLEB) input is in-
active, it selects the data and clock from the parallel
to serial converter block. When LLEB is active, it
forces the output data multiplexer to select the data
and clock from the RSD and Receive Serial Clock
(RSCLK) inputs, and a receive-to-transmit loopback
can be established at the serial data rate.
Loop Timing
In Serial Loop Timing (SLPTIME) mode, the clock
synthesizer PLL of the S3055 is bypassed, and the
timing of the entire transmitter section is controlled
by the Receive Serial Clock, RSCLKP/N. This mode
is entered by setting the SLPTIME input to a TTL
high level.
In this mode, the REFCLKP/N input is not used to
generate TSCLKP/N. It should be carefully noted
that the internal PLL and CDR PLL continue to op-
erate in this mode, and continue as the source for
the 155/77MCK and RSD/RSCLK, and if these sig-
nals are being used, the REFCLKP/N input must be
properly driven.
In Reference Loop Timing (RLPTIME) mode, the
Parallel Output Clock (POCLK) from the receiver is
used as the reference clock to the transmitter. The
155/77MCK are generated from the POCLK in this
operating mode.
January 31, 2002 / Revision D