IDT82P2284 Integrated Device Technology, Inc., IDT82P2284 Datasheet - Page 303

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IDT82P2284

Manufacturer Part Number
IDT82P2284
Description
4 Channel T1/J1/E1 Transceiver
Manufacturer
Integrated Device Technology, Inc.
Datasheet

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IDT82P2284
E1 Error Insertion (06FH, 16FH, 26FH, 36FH)
CRCINV:
CRCPINV:
CASPINV:
NFASINV:
FASALLINV:
FAS1INV:
Programming Information
Bit Name
Default
Bit No.
Type
This bit is valid when the CRC Multi-frame or the Modified CRC Multi-frame is generated.
A transition from ‘0’ to ‘1’ on this bit will invert all 4 calculated CRC bits in one Sub-Multi-Frame.
This bit is cleared when the inversion is completed.
This bit is valid when the CRC Multi-frame is generated.
A transition from ‘0’ to ‘1’ on this bit will invert one 6-bit CRC Multi-Frame alignment pattern (‘001011’).
This bit is cleared when the inversion is completed.
This bit is valid when the CAS Multi-frame is generated.
A transition from ‘0’ to ‘1’ on this bit will invert one 4-bit Signaling Multi-Frame alignment pattern (‘0000’).
This bit is cleared when the inversion is completed.
This bit is valid when the Basic frame is generated.
A transition from ‘0’ to ‘1’ on this bit will invert one NFAS bit (the Bit 2 of TS0 of each odd frame).
This bit is cleared when the inversion is completed.
This bit is valid when the Basic frame is generated.
A transition from ‘0’ to ‘1’ on this bit will invert one 7-bit FAS pattern (the Bit 2 ~ Bit 8 of TS0 of each even frame).
This bit is cleared when the inversion is completed.
This bit is valid when the Basic frame is generated.
A transition from ‘0’ to ‘1’ on this bit will invert one FAS bit (the Bit 2 ~ Bit 8 of TS0 of each even frame).
This bit is cleared when the inversion is completed.
7
Reserved
6
CRCINV
R/W
5
0
CRCPINV
R/W
4
0
292
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
CASPINV
R/W
3
0
NFASINV
R/W
2
0
FASALLINV
R/W
1
0
March 22, 2004
FAS1INV
R/W
0
0

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