IDT82P2284 Integrated Device Technology, Inc., IDT82P2284 Datasheet - Page 368
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IDT82P2284
Manufacturer Part Number
IDT82P2284
Description
4 Channel T1/J1/E1 Transceiver
Manufacturer
Integrated Device Technology, Inc.
Datasheet
1.IDT82P2284.pdf
(384 pages)
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IDT82P2284
7.4
7.5
Physical And Electrical Specifications
The capacitive loading for timing measurement is:
100 pF for BUS: D[7:0],
50 pF for other pins.
The timing can be applied to both clock edges as defined by active clock edge selection.
Delays are measured according to the cross of 50% of the rising/falling edge.
The duty cycle for TSCKn/MTSCK & RSCKn/MRSCK is from 40% to 60%.
The system Input / Output timing in is listed as below:
- Relative to nominal rate
DIGITAL I/O TIMING CHARACTERISTICS
CLOCK FREQUENCY REQUIREMENT
Note:
* The ‘-10’ applies to the case that the clock is input and the ‘0’ applies to the case that the clock is output.
Symbol
Tprop
Thold
Ts
Propagation Delay
Set Up Time
Parameter
Hold Time
TSCK
RSCK
Outputs
Inputs
RSCK
TSCK
OSCI
Figure 42. I/O Timing in Mode
-10 / 0 *
Min.
10
10
-100
-100
Min
-32
Ts
Tprop
Thold
357
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
+100
+100
Max
+32
Typ.
Unit
ppm
ppm
ppm
Max
20
Unit
ns
ns
ns
March 22, 2004
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