IDT82P2284 Integrated Device Technology, Inc., IDT82P2284 Datasheet - Page 73

• Manufacturer Part Number: IDT82P2284
• Description: 4 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2284
3.18
the device. The data input to the four links can be aligned with each
other or input independently. The timing clocks and framing pulses can
be provided by the system backplane or obtained from the processed
data of each link. The Transmit System Interface supports various con-
figurations to meet various requirements in different applications.
3.18.1
multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode,
the TSDn pin is used to input the data to each link at the bit rate of 1.544
Mb/s or 2.048 Mb/s (T1/J1 mode E1 rate). While in the Multiplexed
Mode, the data is byte-interleaved from one high speed data stream and
inputs on the MTSDA1 (MTSDB1) pins at the bit rate of 8.192 Mb/s. The
demultiplexed data input to the four links is 2.048 Mb/s on the system
side and converted into 1.544 Mb/s format to the device.
the transmit line side are timed to a same clock source, the Transmit
System Interface is in Transmit Clock Master mode. If the transmit sys-
tem interface and the transmit line side are timed to different clock
Table 42: Operating Modes Selection In T1/J1 Transmit Path
3.18.1.1
signal on the TSCKn pin and framing pulse on the TSFSn pin to input
the data on each TSDn pin. The signaling bits on the TSIGn pin are per-
channel aligned with the data on the TSDn pin.
face is clocked by the TSCKn. The active edge of the TSCKn used to
update the pulse on the TSFSn is determined by the FE bit. The active
edge of the TSCKn used to sample the data on the TSDn and TSIGn is
NOTE:
1. When the G56K, GAP bits in TPLC indirect registers are set, the PCCE bit must be set to ‘1’.
2. The MAP[1:0] bits can not be set to ‘00’ in the Transmit Multiplexed mode.
3. In Transmit Multiplexed mode, two sets of multiplexed data and signaling pins (A and B) are provided for one multiplexed bus. Their functions are the same. One is the backup for the
other. One set is selected by the MTSDA bit when used.
TMUX TMODE
0
1
The Transmit System Interface determines how to input the data to
In T1/J1 mode, the Transmit System Interface can be set in Non-
In the Non-multiplexed mode, if the transmit system interface and
In the Transmit Clock Master mode, each link uses its own timing
In the Transmit Clock Master mode, the data on the system inter-
TRANSMIT SYSTEM INTERFACE
X
0
1
T1/J1 MODE
Transmit Clock Master Mode
G56K, GAP /
not all 0s
FBITGAP
00 / 0
X
X
1
MAP[1:0]
00
01
10
01
10
11
11
X
2
Transmit Clock Master Full T1/J1
Transmit Clock Master Fractional T1/J1
Transmit Clock Slave - T1/J1 Rate
Transmit Clock Slave - T1/J1 Mode E1 Rate per G.802
Transmit Clock Slave - T1/J1 Mode E1 Rate per One Filler Every
Four CHs
Transmit Clock Slave - T1/J1 Mode E1 Rate per Continuous CHs
Transmit Multiplexed - T1/J1 Mode E1 Rate per G.802
Transmit Multiplexed - T1/J1 Mode E1 Rate per One Filler Every
Four CHs
Transmit Multiplexed - T1/J1 Mode E1 Rate per Continuous CHs
Operating Mode
62
sources, the Transmit System Interface is in Transmit Clock Slave
mode.
the entire T1/J1 frame, the Transmit System Interface is in Transmit
Clock Master Full T1/J1 mode. If only the clocks aligned to the selected
channels are output on TSCKn, the Transmit System Interface is in
Transmit Clock Master Fractional T1/J1 mode.
equal to 1.544 Mb/s (i.e., the line data rate) or 2.048 Mb/s. If the back-
plane data rate is 2.048 Mb/s, the Transmit System Interface is in T1/J1
mode E1 rate and the data to be transmitted should be mapped to 1.544
Mb/s per 3 kinds of schemes.
rate on the system side (2.048 Mb/s) should be mapped to the data rate
in the line side (1.544 Mb/s), there are still 3 kinds of schemes to be
selected.
each link into various operating modes and the pins’ direction of the
transmit system interface in different operating modes.
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the TSFSn is ahead.
F-bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. The
indications are selected by the FSTYP bit. The active polarity of the
TSFSn is selected by the FSINV bit.
mit Clock Master Full T1/J1 mode and Transmit Clock Master Fractional
T1/J1 mode.
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
In the Transmit Clock Master mode, if TSCKn outputs pulses during
In the Transmit Clock Slave mode, the backplane data rate may be
In the Transmit Multiplexed mode, since the demultiplexed data
Table 42 summarizes how to set the transmit system interface of
In the Transmit Clock Master mode, the TSFSn can indicate each
The Transmit Clock Master mode includes two sub-modes: Trans-
TSDn, TSIGn, TSCKn, TSFSn
MTSCK, MTSFS, MTSDA[1],
MTSIGA[1] (MTSDB[1],
Transmit System Interface Pin
TSDn, TSIGn
MTSIGB[1])
Input
3
March 22, 2004
TSCKn, TSFSn
Output
X
X