IDT82P2284 Integrated Device Technology, Inc., IDT82P2284 Datasheet - Page 34

• Manufacturer Part Number: IDT82P2284
• Description: 4 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2284
3.8
3.8.1
ment patterns in the standard Super-Frame (SF), Extended Super-
Frame (ESF), T1 Digital Multiplexer (DM) or Switch Line Carrier - 96
(SLC-96) framing formats. The T1 DM and SLC-96 formats are only sup-
ported in T1 mode. The Frame Processor acquires frame alignment per
ITU-T requirement.
ues to monitor the received data stream. The Frame Processor will
declare framing bit errors or bit error events if any. The Frame Processor
can also detect out-of-frame events based on selected criteria.
bit.
Functional Description
Table 12: The Structure of SF
Note:
‘X’ should be logic 0 in T1 FAS.
‘X’ can be logic 0 or 1 in J1 FAS because this position is used as Yellow Alarm Indication bit.
In T1/J1 mode, the Frame Processor searches for the frame align-
When frame alignment is achieved, the Framer Processor contin-
The Frame Processor can also be bypassed by setting the UNFM
Frame No. In The SF
FRAME PROCESSOR
T1/J1 MODE
10
11
12
1
2
3
4
5
6
7
8
9
Ft
1
0
1
0
1
0
F-Bit (Frame Alignment)
Fs
23
X
0
0
1
1
1
3.8.1.1
3.8.1.1.1
up of 12 frames. Each frame consists of one overhead bit (F-bit) and 24
8-bit channels. Its Frame Alignment Pattern is ‘100011011100’ for T1
and ‘10001101110X’ for J1 located in the F-bit position. The same pat-
tern is a mimic pattern if it is received in the data stream other than F-bit.
The synchronization criteria of SF format is selected by the MIMICC bit.
When the MIMICC bit is set to ‘1’, the SF synchronization is acquired if
two consecutive Frame Alignment Patterns are received error free in the
data stream without a mimic pattern. When the MIMICC bit is set to ‘0’,
the SF synchronization is acquired if two consecutive Frame Alignment
Patterns are received error free in the data stream. In this case, the
existence of mimic patterns is ignored. If a mimic pattern exists during
the frame searching procedure, the MIMICI bit will be set to indicate the
presence of a mimic pattern.
RMFBI bit is set at the first bit of each SF frame.
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
The structure of T1/J1 SF is illustrated in Table 12. The SF is made
The SF synchronization is indicated by ‘0’ in the OOFV bit. The
Synchronization Searching
Super Frame (SF) Format
Data Bit
1 - 8
1 - 8
1 - 8
1 - 8
1 - 8
1 - 7
1 - 8
1 - 8
1 - 8
1 - 8
1 - 8
1 - 7
The Bit In Each Channel
Signaling Bit
A (bit 8)
B (bit 8)
March 22, 2004
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