IDT82P2284 Integrated Device Technology, Inc., IDT82P2284 Datasheet - Page 62

• Manufacturer Part Number: IDT82P2284
• Description: 4 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2284
3.15.2
(refer to Figure 11), which are Channel Associated Signalings (CAS).
The signaling codewords (ABCD) are clocked out on the RSIGn/
MRSIGA(MRSIGB) pins. They are in the lower nibble of the timeslot with
its corresponding data serializing on the RSDn/MRSDA(MRSDB) pins
(as shown in Figure 16).
sponding timeslot are extracted to the A,B,C,D bits in the Extracted Sig-
naling Data/Extract Enable register. The data in the A,B,C,D bits in the
register are the data to be output on the RSIGn/MRSIGA(MRSIGB) pins.
The bits corresponding to TS0 and TS16 output on the RSIGn/
MRSIGA(MRSIGB) pins are Don’t-Care.
Thus, the A,B,C,D bits in the Extracted Signaling Data/Extract Enable
register are updated only if 2 consecutive received ABCD codewords of
the same timeslot are identical.
frame synchronization, out of Signaling multi-frame synchronization or
Functional Description
MRSIGA(MRSIGB)
MRSDA(MRSDB)
In Signaling Multi-Frame, the signaling bits are located in TS16
When the EXTRACT bit is set to ‘1’, the signaling bits in its corre-
Signaling de-bounce will be executed when the DEB bit is set to ‘1’.
Signaling freezing is performed automatically when it is out of Basic
MRSIGA(MRSIGB)
MRSDA(MRSDB)
RSIGn/
RSDn/
E1 MODE
RSIGn/
RSDn/
1 2 3 4 5 6 7 8
1 2 3 4 5 6 78
Channel 24
TS31
ABCD
A B C D
1 2 3 4 5 6 78 1 2 3 4 5 6 78
TS0
F-bit
Figure 15. Signaling Output In T1/J1 Mode
F
Figure 16. Signaling Output In E1 Mode
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Channel 1
TS1
ABCD
A B C D
1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78
51
TS15
Channel 2
slips occurs in the Elastic Store Buffer. It is also performed when the
FREEZE bit is set to ‘1’. The signaling freezing freezes the signaling
data in the A,B,C,D bits in the Extracted Signaling Data/Extract Enable
register as the previous valid value.
Extracted Signaling Data/Extract Enable register are changed, it is cap-
tured by the corresponding COSI[X] bit (1 ≤ X ≤ 30). When the SIGE bit
is set to ‘1’, any one of the COSI[X] bits being ‘1’ will generate an inter-
rupt and will be reported by the INT pin.
of the Receive CAS/RBS Buffer. They are accessed by specifying the
address in the ADDRESS[6:0] bits. Whether the data is read from or
written into the specified indirect register is determined by the RWN bit
and the data is in the D[7:0] bits. The access status is indicated in the
BUSY bit. Refer to Chapter 4.5 Indirect Register Access Scheme for
details about the indirect registers write/read access.
ABCD
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Each time the extracted signaling bits in the A,B,C,D bits in the
The EXTRACT bit and the A,B,C,D bits are in the indirect registers
A B C D
TS16
1 2 3 4 5 6 7 8
TS17
ABCD
Channel 24
A B C D
1 2 3 4 5 6 78 1 2 3 4 5 6 78
TS31
F-bit
ABCD
F
1 2 3 4 5 6 7 8
Channel 1
March 22, 2004
TS0
A B C D