IDT82P2284 Integrated Device Technology, Inc., IDT82P2284 Datasheet - Page 75

• Manufacturer Part Number: IDT82P2284
• Description: 4 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2284
pin and the framing pulse on the TSFSn pin to input the data on the
TSDn pin are provided by the system side. When the TSLVCK bit is set
to ‘0’, each link uses its own TSCKn and TSFSn; when the TSLVCK bit
is set to ‘1’ and all four links are in the Transmit Clock Slave mode, the
four links use the TSCK[1] and TSFS[1] to input the data. The signaling
bits on the TSIGn pin are per-channel aligned with the data on the TSDn
pin.
is clocked by the TSCKn. The active edge of the TSCKn used to sample
the pulse on the TSFSn is determined by the FE bit. The active edge of
the TSCKn used to sample the data on the TSDn and TSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the TSFSn is ahead. The data rate of the system side is 1.544 Mb/s
or 2.048 Mb/s. When it is 2.048 Mb/s, the TSCKn can be selected by the
CMS bit to be the same rate as the data rate on the system side (2.048
MHz) or double the data rate (4.096 MHz). If all four links use the
TSCK[1] and TSFS[1] to input the data, the CMS bit of the four links
should be set to the same value. If the speed of the TSCKn is double the
data rate, there will be two active edges in one bit duration. In this case,
the EDGE bit determines the active edge to sample the data on the
TSDn and TSIGn pins. The pulse on the TSFSn pin is always sampled
on its first active edge.
bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. The
indications are selected by the FSTYP bit. The active polarity of the
TSFSn is selected by the FSINV bit. If the pulse on the TSFSn pin is not
an integer multiple of 125 µs, this detection will be indicated by the
TCOFAI bit. If the TCOFAE bit is enabled, an interrupt will be reported by
the INT pin when the TCOFAI bit is ‘1’.
3.18.1.3
rate on the system side (2.048 Mb/s) should be mapped to the data rate
in the line side (1.544 Mb/s), 3 kinds of schemes should be selected by
the MAP[1:0] bits. The schemes per G.802, per One Filler Every Four
CHs and per Continuous CHs are the same as the description in
Chapter 3.18.1.2 Transmit Clock Slave Mode.
1.544
2.048
Mb/s
Mb/s
discarded
In the Transmit Clock Slave mode, the timing signal on the TSCKn
In the Transmit Clock Slave mode, the data on the system interface
In the Transmit Clock Slave mode, the TSFSn can indicate each F-
In the Transmit Multiplexed mode, since the demultiplexed data
Transmit Multiplexed Mode
TS0
the 8th bit
F
CH1
TS1
Figure 26. E1 To T1/J1 Format Mapping - Continuous Channels Mode
CH2
TS2
TS3
CH3
TS23
CH23
TS24
64
CH24
transmit the data to all four links. The data of Link 1 to Link 4 is byte-
interleaved input from the multiplexed bus 1. When the data on the mul-
tiplexed bus is input to four links, the sequence of the data is arranged
by setting the channel offset. The data to different links from one multi-
plexed bus must be shifted at a different channel offset to avoid data
mixing.
pin and the framing pulse on the MTSFS pin are provided by the system
side and common to all four links. The signaling bits on the MTSIGA
(MTSIGB) pin are per-channel aligned with the corresponding data on
the MTSDA (MTSDB) pin.
is clocked by the MTSCK. The active edge of the MTSCK used to sam-
ple the pulse on the MTSFS is determined by the FE bit. The active
edge of the MTSCK used to sample the data on the MTSDA (MTSDB)
and MTSIGA (MTSIGB) is determined by the DE bit. The FE bit and the
DE bit of the four links should be set to the same value respectively. If
the FE bit and the DE bit are not equal, the pulse on the MTSFS is
ahead. The MTSCK can be selected by the CMS bit to be the same rate
as the data rate on the system side (8.192 MHz) or double the data rate
(16.384 MHz). The CMS bit of the four links should be set to the same
value. If the speed of the MTSCK is double the data rate, there will be
two active edges in one bit duration. In this case, the EDGE bit deter-
mines the active edge to sample the data on the MTSDA (MTSDB) and
MTSIGA (MTSIGB) pins. The pulse on the MTSFS pin is always sam-
pled on its first active edge.
bit of the first link or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-
frame of the first link. The indications are selected by the FSTYP bit. The
active polarity of the MTSFS is selected by the FSINV bit. The FSTYP
bit and the FSINV bit of the four links should be set to the same value. If
the pulse on the MTSFS pin is not an integer multiple of 125 µs, this
detection will be indicated by the TCOFAI bit. If the TCOFAE bit is
enabled, an interrupt will be reported by the INT pin when the TCOFAI
bit is ‘1’.
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
discarded
TS25~TS31
In the Transmit Multiplexed mode, one multiplexed bus is used to
In the Transmit Multiplexed mode, the timing signal on the MTSCK
In the Transmit Multiplexed mode, the data on the system interface
In the Transmit Multiplexed mode, the MTSFS can indicate each F-
F
CH1
discarded
TS0
CH2
the 8th bit
TS1
TS2
CH24
March 22, 2004
F CH1
TS24