S2052 AMCC (Applied Micro Circuits Corp), S2052 Datasheet

S2052

Manufacturer Part Number

S2052

Description

Bicmos Pecl Clock Generator Fibre Channel And Gigabit Ethernet Transceiver

Manufacturer

AMCC (Applied Micro Circuits Corp)

Datasheet

1.S2052.pdf (15 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

S2052B

Manufacturer:

XILINX

Company:

BOSTOCK HK LIMITED

Part Number:

S2052B

Manufacturer:

Company:

Meier Automation Equipment Co., Limited

Part Number:

S2052B

Manufacturer:

Quantity:

20 000

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

S2052C

Manufacturer:

ASICEN

Quantity:

Current page: 1 of 15
Download datasheet (153Kb)

FEATURES

APPLICATIONS

High-speed data communications

Figure 1. System Block Diagram

DEVICE

SPECIFICATION

April 29, 1999 / Revision E

BiCMOS PECL CLOCK GENERATOR

• Functionally compliant with ANSI X3T11 Fibre

• Transmitter incorporates phase-locked loop

• Receiver PLL configured for clock and data

• 1250 and 1062 Mb/s operation

• 10-bit parallel TTL compatible interface

• 800mW typical power dissipation

• +3.3V power supply

• Low-jitter serial PECL compatible interface

• Lock detect

• Local loopback

• 64 PQFP package

• Fibre Channel framing performed by receiver

• Continuous downstream clocking from receiver

• Drives 30m of Twinax cable directly

• Workstation

• Frame buffer

• Switched networks

• Data broadcast environments

FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER

Channel physical and transmission protocol

standards and IEEE 802.3Z Gigabit Ethernet

Applications

(PLL) providing clock synthesis from low-speed

reference

recovery

Controller

Ethernet

Gigabit

S2052

Control

S2036

(OFC)

Open

Fiber

Optical

GENERAL DESCRIPTION

The S2052 transmitter and receiver chip is designed

to perform high-speed serial data transmission over

fiber optic or coaxial cable interfaces conforming to

the requirements of the ANSI X3T11 Fibre Channel

specification. The chip runs at 1250.0, and 1062.5

Mbit/s data rates with associated 10-bit data word.

The chip performs parallel-to-serial and serial-to-par-

allel conversion and framing for block-encoded data.

The transmitter’s on-chip PLL synthesizes the high-

speed clock from a low-speed reference. The

receiver’s on-chip PLL synchronizes directly to incom-

ing digital signal to receive the data stream. The

transmitter and receiver each support differential

PECL-compatible I/O for fiber optic component inter-

faces, to minimize crosstalk and maximize data

integrity. Local loopback mode is provided for system

diagnostics.

Figure 1 shows a typical configuration incorporating

the chip, which is compatible with AMCC’s S2036

Open Fiber Control (OFC) device.

Optical

• Proprietary extended backplanes

• RAID drives

• Mass storage devices

Optical

S2052

Control

S2036

(OFC)

Open

Fiber

Controller

Ethernet

Gigabit

S2052

Related parts for S2052

Related keywords

S2052 datasheet
S2052 data sheet
S2052 pdf datasheet
S2052 component
S2052 part
S2052 distributor
S2052 RoHS
S2052 datasheet download