S2052 AMCC (Applied Micro Circuits Corp), S2052 Datasheet - Page 2

• Manufacturer Part Number: S2052
• Description: Bicmos Pecl Clock Generator Fibre Channel And Gigabit Ethernet Transceiver
• Manufacturer: AMCC (Applied Micro Circuits Corp)

Figure 3. Functional Block Diagram
2
S2052 OVERVIEW
The S2052 transmitter and receiver provide serializa-
tion and deserialization functions for block-encoded
data to implement a Fibre Channel interface. Opera-
tion of the S2052 is straightforward, as depicted in
Figure 2. The sequence of operations is as follows:
Transmitter
Receiver
The 10-bit parallel data handled by the S2052 device
should be from a DC-balanced encoding scheme, such
as the 8B/10B transmission code, in which informa-
tion to be transmitted is encoded 8 bits at a time into
10-bit transmission characters
ANSI X3.230 FC-PH (Fibre Channel Physical and Sig-
naling Interface).
S2052
1. 10-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
1. Clock and data recovery from serial input
2. Serial-to-parallel conversion
3. Frame detection
4. 10-bit parallel output
TXTESTN
-LCK_REF
EN_CDET
TX [0:9]
RXBYPN
EWRAP
TBC
RXN
RXP
TN
TP
1
, and be compliant with
CONTROL
10
LOGIC
2:1
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
D
Latch
Input
Q
MULTIPLIER
F 0 = F 1 X 10
PLL CLOCK
RECOVERY
PLL CLOCK
10
REGISTER
Figure 2. Interface Diagram
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figure 4. A block diagram showing the basic chip
operation is shown in Figure 3.
Loopback
Local loopback is supported by the chip, and pro-
vides a capability for performing offline testing of the
interface to ensure the integrity of the serial channel
before enabling the transmission medium. It also al-
lows for system diagnostics.
Data Out
SHIFT
Parallel
BITCLK
Data In
Serial
TBC
D
REGISTER
SHIFT
COM_DET
DETECT
LOGIC
D
Transceiver
S2052
Q
10
April 29, 1999 / Revision E
RX[0:9]
COM_DET
RBC1
RBC0
TXP
TXN
RBC
COM_DET
Serial
Data In
Parallel
Data Out