L64733 LSI Logic Corporation, L64733 Datasheet - Page 16

• Manufacturer Part Number: L64733
• Description: Tuner/receiver Chipset
• Manufacturer: LSI Logic Corporation

Control Signals Interface
16
PLLVDD
PLLVSS
The Control Signals interface controls the operation of the L64734; it is
not associated with any particular interface.
IDDTn
RESET
XCTR_IN
XCTR[3]
XCTR[2:0]
L64733/L64734 Tuner and Satellite Receiver Chipset
PLL Power
PLLVDD is the power supply pin for the PLL module; it is
normally connected to the system power (V
PLL Ground
PLLVSS is the ground pin for the PLL module; it is
normally connected to the system ground plane.
Test
The IDDTn pin is an LSI Logic internal test pin. Tie the
IDDTn pin LOW for normal operation.
Reset
This active-HIGH signal resets all internal data paths.
Reset timing is asynchronous to the device clocks. Reset
does not affect the configuration registers.
Control Input
The XCTR_IN pin is an external input control pin. It is
sensed by reading the XCTR_IN register bit.
Control Output/Sync Status Flag
This signal indicates the synchronization status for one of
three synchronization modules in the L64734 or the
XCTR[3] field in Group 4, APR 55. The modules are the
Viterbi decoder, Reed-Solomon deinterleaver (DI/RS),
and descrambler. For any of the three synchronization
outputs, asserting the XCTR[3] signal indicates that
synchronization has been achieved for the sync module
chosen using the SSS[1:0] register bits. When
deasserted, the signal indicates an out-of-
synchronization condition.
Control Output
The XCTR[2:0] pins are external output control pins.
They are set by programming particular register bits.
XCTR[2] is mapped to CPG1, and XCTR[0] is multiplexed
with CPG2, when used with the L64733 Tuner IC. When
the on-chip serializer is used to generate a serial 2- or
3-wire protocol on the XCTR[2:0] pins, the mapping is
XCTR[2] = EN, XCTR[1] = SCL, and XCTR[0] = SDA.
DD
) plane.
Output
Output
Input
Input
Input
Input
Input