L64733C LSI Logic Corporation, L64733C Datasheet - Page 20
L64733C
Manufacturer Part Number
L64733C
Description
Tuner And Satellite Receiver Chipset Data Sheet 2/01
Manufacturer
LSI Logic Corporation
Datasheet
1.L64733C.pdf
(52 pages)
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Microcontroller Interface
Synthesizer Control Interface
20
FSTARTOUT Frame Start Output
The Microcontroller Interface connects the L64734 to an external
microcontroller.
INTn
SADR[1:0]
SCLK
SDATA
The Synthesizer Control Interface allows the L64734 to control the
L64733C frequency synthesizer.
FDOUB
L64733C/L64734 Tuner and Satellite Receiver Chipset
The L64734 asserts the FSTARTOUT signal during the
first bit of every frame with valid data in Serial Channel
Output mode and during the first byte in Parallel Channel
Output mode. FSTARTOUT is valid only when the
DVALIDOUT signal is asserted. The FSTARTOUT signal
is deasserted after the FEC_RST register bit is set.
Interrupt
The L64734 asserts INTn when an internal unmasked
interrupt flag is set. The INTn signal remains asserted
during the interrupt condition, and the interrupt flag is not
masked.
Serial Address
The SADR[1:0] signals are the two programmable bits of
the serial address for the L64734.
Serial Clock
SCLK is the serial clock pin for a two-wire serial protocol.
Serial Data
SDATA is the serial data pin for a two-wire serial protocol.
Frequency Doubler
Bit 6 of register Group 4, APR 79 controls the L64734
FDOUB output pin, which enables or disables the
frequency doubler on the L64733C.
Output, 3-State
Bidirectional
Bidirectional
Output
Output
Input
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