L64733C LSI Logic Corporation, L64733C Datasheet - Page 6
L64733C
Manufacturer Part Number
L64733C
Description
Tuner And Satellite Receiver Chipset Data Sheet 2/01
Manufacturer
LSI Logic Corporation
Datasheet
1.L64733C.pdf
(52 pages)
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Features and Benefits
System Features
Chipset Features
6
The following subsections provide a list of system and chipset features.
L64733C/L64734 Tuner and Satellite Receiver Chipset
Direct down-conversion
Integrated programmable cut-off low-pass filters for variable-rate
operation
Dual AGC for optimizing performance with respect to intermodulation
and noise
Integrated synthesizer
Integrated quadrature amplitude and phase imbalance compensation
RF Loop-Through
DVB and DSS system specifications support
BPSK/QPSK demodulation rates from 1 to 45 Mbaud
Matched filter (square root raised cosine filter with roll off factor of
20% or 35%)
Antialiasing filters for operation from 1 to 45 MBaud without switching
external SAW filters or the need for low-pass filters
On-chip digital clock synchronization
On-chip digital carrier synchronization, featuring a frequency sweep
capability for signal acquisition
Autoacquisition demodulator mode and tuner control through an
on-chip microcontroller
Integrated Phase-Locked Loop (PLL) for clock synthesis, allowing the
use of a fundamental mode crystal
Fast channel switching mode
Power estimation for AGC
Programmable Viterbi decoder module for rates 1/2, 2/3, 3/4, 5/6, 6/7,
and 7/8
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