L64733C LSI Logic Corporation, L64733C Datasheet - Page 41

• Manufacturer Part Number: L64733C
• Description: Tuner And Satellite Receiver Chipset Data Sheet 2/01
• Manufacturer: LSI Logic Corporation

Table 12
1. Minimum Fs (sampling clock = 30 MHz).
L64733C/L64734 Tuner and Satellite Receiver Chipset
Parameter
10
11
12
1
2
3
4
5
6
6
7
8
9
t
t
t
t
t
t
t
t
t
t
T
t
t
CYCLE_PS
CYCLE
PWH
PWL
S
H
ODS
ODP
RWH
WK
PWH_PS
PWL_PS
DLY
L64734 AC Timing Parameters
Clock Cycle for PCLK
Clock Pulse Width HIGH
Clock Pulse Width LOW
Input Setup Time to CLK
Input Hold to CLK
Output Delay from PCLK, serial
mode
Output Delay from BCLKOUT,
parallel mode
Reset Pulse Width HIGH
Wake-Up Time
Delay from COEn
Clock Cycle for PSOUTp,
PSOUTn clock
PSOUT Clock Pulse Width HIGH
PSOUT Clock Pulse Width LOW
Description
11.1 33.3
Min
280
14
90 MHz
6
5
4
4
3
3
3
–
6
6
Max
35
–
–
–
–
8
–
–
–
6
–
–
1
CLK cycles
CLK cycles
cycles
PCLK
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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