L64780 LSI Logic Corporation, L64780 Datasheet - Page 46

• Manufacturer Part Number: L64780
• Description: Dvb-t Cofdm Demodulator Technical Manual 2/00
• Manufacturer: LSI Logic Corporation

3.2.1 Access to Timing and DDFS Blocks
Figure 3.16 Timing and DDFS Input Mapping
3.2.2 Access to the AFC Block
Figure 3.17 AFC Input Mapping
3-10
26
0
26
0
START DV
START
25
25
24 23
DV
24
0
23
When selecting access to the Timing and DDFS blocks, the CLKMUXIN
signal is configured as an 18 MHz clock (more precisely, four times the
low IF). The DDFS block is the digital rotator that performs the carrier
frequency compensation.
The signals on the bus are I and Q data (in two’s complement format),
a start pulse (START), and a data valid signal (DV). These signals are
mapped on the MUXINBUS. See
In this mode, you can select whether the start pulse comes from the
MUXINBUS or from the Timing recovery unit. The start pulse delimits
every COFDM symbol. This selection is done through the DDFS_MODE
bit (address 0x9, bit 1). If DDFS_MODE = 0, the start pulse comes from
the test bus (test mode); otherwise, the Timing block delivers the start
pulse. Note that this mode could correspond to an external down-
converter that feeds the I and Q data directly into the Timing and DFFS
blocks.
The AFC block performs the estimation of the carrier frequency drift and
produces an analog or digital feedback control signal to compensate for
this drift. In this mode, the CLKMUXIN signal is configured as a 36 MHz
clock (more precisely, eight times the low IF).
The signals on the bus are I and Q data (in two’s complement format),
a start pulse (START), a data valid (DV) signal, and the COFDM symbol
number (S_NB). These signals are mapped on the MUXINBUS.
See
Interfaces
S_NB
21 20
Figure
22
21
0
3.17.
20
Q[9:0]
Q[9:0]
Figure
11 10 9
0
11
3.16.
10
0
9
I[9:0]
I[9:0]
0
0