L64780 LSI Logic Corporation, L64780 Datasheet - Page 95

• Manufacturer Part Number: L64780
• Description: Dvb-t Cofdm Demodulator Technical Manual 2/00
• Manufacturer: LSI Logic Corporation

CLK18
CLKOUT54
DIGIN[9:0]
DVOUT
DVOUT_LP
IBIAS
RESET
SD0[3:0]
SD1[3:0]
STARTOUT
Main Signals
18 MHz Clock
This is the 18 MHz input clock coming from the external
VCXO.
54 MHz Clock
This is the 54 MHz clock output and is used to clock the
L64705 or the L64724.
Digital Inputs
Digital inputs in normal mode when a 10-bit off-chip ADC
is used. DIGIN0 represents the LSB, while DIGIN9
represents the MSB. This bus is latched with the CLK18
clock. In MUXIN mode, DIGIN[9:0] represents the 10
LSBs of the 27 MUXIN bits, with DIGIN[0] mapped to
MUXIN0, and DIGIN9 to MUXIN9. For an on-chip ADC,
this bus must be connected to ground.
SD0 Data Valid Out
When asserted HIGH, this signal validates the SD0[3:0]
bus.
SD1 Data Valid Out
When asserted HIGH, this signal validates the SD1[3:0]
bus.
Input Bias Current for Internal ADC
When not used, this pin must be connected to ground.
Reset
Hard reset. This pin is activ
“Reset AC Timing Parameters,” page
mum and maximum assertion time for a valid res
SD0 Bus
The first 4-bit output bus used to output the high- and
low-priority streams.
SD1 Bus
The second 4-bit output bus used to output the high- and
low-priority streams.
First Soft Decision Mark
When asserted HIGH, this signal marks the first soft
decision of an COFDM symbol to be presented off-chip.
e-HIGH. See
6-5, for the mini-
Section Table 6.6,
O 3-State
O 3-State
O 3-State
O 3-State
O 3-State
et.
5-5
O
I
I
I
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