L64780 LSI Logic Corporation, L64780 Datasheet - Page 93

• Manufacturer Part Number: L64780
• Description: Dvb-t Cofdm Demodulator Technical Manual 2/00
• Manufacturer: LSI Logic Corporation

5.2 Microprocessor Interface
This section lists and describes the microprocessor interface signals.
Note that the parallel interface mode is used for LSI Logic internal testing
and is not intended for use in customer production receivers. The serial
mode interface is used for production systems.
A[4:0]
ASn
CSn
D[7:0]
DTACKn
Microprocessor Interface
Address Bus
The DTTV receiver has a five-bit address bus, A[4:0], that
is used with an eight-bit data bus, D[7:0], a read/write
strobe, Read, an address strobe, ASn, and a chip select
strobe, CSn, to read and write internal registers. The
address lines select internal registers. In Serial Mode, A0
is used as the serial clock, and A[4:1] must be connected
to ground.
Address Strobe
Active LOW address strobe input. Latches the address
on the A[4:0] bus on the falling edge. In Serial interface
mode, ASn must be connected to VDD.
Chip Select
Active LOW chip select strobe input. During a read cycle,
CSn must be LOW to access the on-chip data registers.
During a read access, the external controller can latch
the data from the DTTV receiver with the rising edge of
CSn. During a write access, CSn must go LOW prior to
data being valid from the external controller to the DTTV
receiver. In Serial Interface mode, CSn must be con-
nected to VDD.
Microprocessor Data Bus
This bidirectional bus is used as an input when data is
written to the chip, and as an output when the chip is
read. When the L64780 is not being read or written to,
the data lines are 3-stated. In Serial Interface Mode, D0
is used as the serial data, and D[7:1] are used for the
programmable Serial Bus interface.
Data Transaction Acknowledge
Active LOW output indicating that the transaction has
been completed. When not driven, the line is open-drain
3-stated.
I/O
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