XR16L788 Exar Corporation, XR16L788 Datasheet - Page 15

• Manufacturer Part Number: XR16L788
• Description: High-performance 3.3V Octal Uart
• Manufacturer: Exar Corporation

XR16L788 OCTAL UART
REV. 1.1.4
- Enable RTS/DTR interrupt through IER bit-6 (after
- Select Hysteresis values when used with program-
Automatic CTS/DSR flow control is used to prevent
data overrun to the remote receiver FIFO. The CTS/
DSR pin is monitored to suspend/restart local trans-
mitter. The flow control features are individually se-
lected to fit specific application requirement (see
Figure 8):
F
4.2.1 Auto CTS/DSR Flow Control
IGURE
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its transmit
shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9), UARTA
re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until next re-
ceive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB with RTSB#
and CTSA# controlling the data flow.
setting EFR bit-4). The UART issues an interrupt
when the RTS#/DTR# pin makes a transition: ISR
bit-5 will be set to 1.
mable RX FIFO trigger levels
8. A
(RXA FIFO
CTSB#
RXA FIFO
Interrupt)
RTSA#
TXB
INTA
UTO
Trigger Reached
Receiver FIFO
Trigger Level
Local UART
Transmitter
Auto CTS
Auto RTS
RTS/DTR
UARTA
Monitor
Data Starts
Receive
Data
Assert RTS# to Begin
AND
1
2
Transmission
Trigger Level
3
4
RX FIFO
CTS/DSR F
RTSA#
TXA
CTSA#
RXA
ON
ON
LOW
5
C
7
RTS High
Threshold
ONTROL
15
6
8
- Select CTS (and RTS) or DSR (and DTR) through
- Enable auto CTS/DSR flow control using EFR bit-7.
- Enable CTS/DSR interrupt through IER bit-7 (after
setting EFR bit-4). The UART issues an interrupt
when the CTS#/DSR# pin makes a transition: ISR
bit-5 will be set to 1, and UART will suspend TX
transmissions as soon as the stop bit of the charac-
ter in process is shifted out. Transmission is re-
sumed after the CTS#/DSR# input returns to logic
0, indicating more data may be sent.
O
OFF
Suspend
MCR bit-2.
PERATION
OFF
RTSB#
CTSB#
RTS Low
Threshold
RXB
TXB
Restart
9
10
11
Trigger Reached
Remote UART
ON
Trigger Level
Receiver FIFO
12
Auto CTS
Auto RTS
Transmitter
UARTB
Monitor
ON
Trigger Level
RX FIFO
R T S C T S 1