XR16L788 Exar Corporation, XR16L788 Datasheet - Page 41

• Manufacturer Part Number: XR16L788
• Description: High-performance 3.3V Octal Uart
• Manufacturer: Exar Corporation

XR17C158
PCI BUS OCTAL UART
REV. 1.1.4
GENERAL DESCRIPTION ............................................................................................... 1
PIN DESCRIPTIONS ....................................................................................................... 3
DESCRIPTION .................................................................................................................. 7
1.0 XR16L788 REGISTERS ......................................................................................................................... 7
2.0 CRYSTAL OSCILLATOR / BUFFER .................................................................................................... 12
3.0 TRANSMIT AND RECEIVE DATA ........................................................................................................ 12
4.0 UART ..................................................................................................................................................... 13
A
NEW F
Figure 1. Block Diagram ......................................................................................................................... 1
Figure 2. Pin Out of the Device .............................................................................................................. 2
ORDERING INFORMATION
Figure 3. The XR16L788 Registers ........................................................................................................ 7
1.1
T
T
Figure 4. The Global Interrupt Registers, INT0, INT1, INT2 and INT3 ................................................... 9
T
Figure 5. Timer/Counter circuit. ............................................................................................................ 10
T
3.1 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR. 12
Figure 6. Typical oscillator connections ................................................................................................ 12
T
4.1 P
Figure 7. Baud Rate Generator ............................................................................................................ 14
T
4.2 A
Figure 8. Auto RTS/DTR and CTS/DSR Flow Control Operation ......................................................... 15
4.3 I
Figure 9. Infrared Transmit Data Encoding and Receive Data Decoding ............................................. 16
4.4 I
Figure 10. Internal Loop Back .............................................................................................................. 17
4.5 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING. ......................................... 17
T
T
EFR B
4.6 T
Figure 11. Transmitter Operation in non-FIFO Mode ........................................................................... 20
Figure 12. Transmitter Operation in FIFO and Flow Control Mode ...................................................... 21
4.7 R
4.8 R
Figure 13. Receiver Operation in non-FIFO Mode ............................................................................... 22
Figure 14. Receiver Operation in FIFO and Flow Control Mode .......................................................... 22
4.9 IER
4.10 IER
4.11 I
T
T
T
T
PPLICATIONS
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
DEVICE CONFIGURATION REGISTER SET ................................................................................... 7
NFRARED
NTERNAL
RANSMITTER
INT0 Channel Interrupt Indicator: ....................................................................................... 9
INT1, INT2 and INT3 Interrupt Source Locator ................................................................. 9
ROGRAMMABLE
UTOMATIC
ECEIVER
EGISTERS
NTERRUPT
8: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. S
1: XR16L788 R
2: D
3: UART C
4: TIMER CONTROL R
5: T
6: T
7: UART CHANNEL CONFIGURATION REGISTERS. ............................................................. 18
IT
9: I
10: T
11: P
12: A
EATURES
VERSUS
-4. ............................................................................................................................................. 19
VERSUS
NTERRUPT
RANSMIT AND
YPICAL DATA RATES WITH A
EVICE
L
M
RANSMIT AND
ARITY SELECTION
UTO
........................................................................................................................................................... 21
OOPBACK
.......................................................................................................................................................... 21
RTS/DTR H
ODE
........................................................................................................................................... 1
S
R
R
: ...................................................................................................................................... 1
TATUS
...................................................................................................................................................... 20
ECEIVE
RS485 H
ECEIVE
C
HANNEL
B
.................................................................................................................................................. 16
ONFIGURATION
AUD
S
R
........................................................................................................................................... 16
OURCE AND
EGISTER
FIFO I
/T
EGISTER
R
............................................................................................................................ 2
R
ARDWARE
ATE
RANSMIT
R
ECEIVE
[7:0] I
ALF
ECEIVE
NTERRUPT
G
................................................................................................................. 26
-
ENERATOR
DUPLEX
EGISTER
(ISR) .................................................................................................................. 23
S
NTERRUPT
ETS
FIFO P
D
F
R
TABLE OF CONTENTS
P
FIFO T
LOW
ATA
EGISTERS
RIORITY
....................................................................................................... 8
14.7456 MH
M
D
R
C
OLLED
ODE
................................................................................................. 10
IRECTION
........................................................................................................... 13
ONTROL
EGISTER
RIGGER
S
L
O
OURCE
EVEL
PERATION
.......................................................................................... 8
M
ODE
O
, 16C550
C
PERATION
L
Z CRYSTAL OR EXTERNAL CLOCK AT
................................................................................ 24
ONTROL
I
EVEL
E
O
NCODING AND
PERATION
.................................................................................. 22
S
ELECTION
........................................................................... 14
COMPATIBLE
D
ELAY FROM
..................................................................... 23
C
..................................................... 25
LEARING
............................................... 13
T
RANSMIT
...................................... 10
HADED BITS ARE ENABLED BY
-
TO
16X S
-R
ECEIVE
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AMPLING
.......... 29
... 14