XR16L788 Exar Corporation, XR16L788 Datasheet - Page 22

• Manufacturer Part Number: XR16L788
• Description: High-performance 3.3V Octal Uart
• Manufacturer: Exar Corporation

The Interrupt Enable Register (IER) masks the inter-
rupts from receive data ready, transmit empty, line
status and modem status registers. These interrupts
are reported in the Interrupt Status Register (ISR)
register and also encoded in INT (INT0-INT3) register
in the Device Configuration Registers.
F
F
4.8.3 Interrupt Enable Register (IER)
IGURE
IGURE
R e ce ive D a ta
B yte a n d E rro rs
(8 X M O D E R e g is te r)
1 6 X o r 8 X S a m p lin g
C lo ck (8 X M O D E R e g .)
a n d E rro rs
D a ta B y te
13. R
1 6 X o r 8 X C lo c k
14. R
R e c e iv e
6 4 b yte s b y 1 1 -
b it w id e F IF O
ECEIVER
ECEIVER
O
O
PERATION IN NON
PERATION IN
LS R bits
F la g s in
R e ce ive D a ta S h ift
E rror
R e g iste r (R S R )
4:2
R e ce ive D a ta
R e c e ive
(6 4 -b yte )
R e c e iv e D a ta S h ift
FIFO
F IF O
D a ta
R e g is te r (R S R )
H o ld in g R e g is te r
-FIFO M
R e c e iv e D a ta
AND
(R H R )
F
D a ta fa lls to 4 0
F IF O T rig g e r= 4 8
D a ta fills to 5 6
V a lid a tio n
LOW
D a ta B it
ODE
E xa m p le :
- F IF O trig g e r le ve l se t a t 4 8 b yte s
- R T S /D T R h ya ste re sis se t a t + /-8 ch a rs.
C
22
ONTROL
When the receive FIFO (FCR BIT-0 = a logic 1) and
receive interrupts (IER BIT-0 = logic 1) are enabled,
the RHR interrupts (see ISR bits 3 and 4) status will
reflect the following:
A. The receive data available interrupts are issued
4.9 IER
R T S # /D T R # re -a s se rts w h e n d a ta fa lls b e lo w
th e trig g e r le v e l to re sta rt re m o te tra n sm itte r.
E n a b le b y E F R b it-6 = 1 , M C R b it-2 .
R T S # /D T R # d e -a sse rts w h e n d a ta fills a b o ve
th e trig g e r le v e l to su sp e n d re m o te tra n sm itte r.
E n a b le b y E F R b it-6 = 1 , M C R b it-2 .
V a lid a tio n
to the host when the FIFO has reached the pro-
D a ta B it
R H R In te rru p t (IS R b it-2 ) is p ro g ra m m e d
a t F IF O trig g e r le ve l (R X T R G ).
F IF O is E n a b le b y F C R b it-0 = 1
O
M
PERATION
ODE
VERSUS
R H R In te rru p t (IS R b it-2 )
R
ECEIVE
XR16L788 OCTAL UART
R e ce ive D a ta C ha ra cte rs
R e c e iv e D a ta C h a ra c te rs
FIFO I
NTERRUPT
R X F IF O 1
R X F IF O 1
REV. 1.1.4
M
ODE