78Q2120 Teridian Semiconductor Corp. (TDK Semiconductor), 78Q2120 Datasheet - Page 17

no-image

78Q2120

Manufacturer Part Number
78Q2120
Description
10/100 Ethernet PHYS
Manufacturer
Teridian Semiconductor Corp. (TDK Semiconductor)
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
78Q2120-64T
Manufacturer:
TDK
Quantity:
561
Part Number:
78Q2120-64T
Manufacturer:
TDK/东电化
Quantity:
20 000
Company:
Part Number:
78Q2120-CGT
Quantity:
2 703
Part Number:
78Q2120C-64CGT/F-R6
Manufacturer:
TDK/东电化
Quantity:
20 000
Part Number:
78Q2120C-64T
Manufacturer:
PANASONIC
Quantity:
2 000
Part Number:
78Q2120C-CGT
Manufacturer:
PHILIPS
Quantity:
10
Part Number:
78Q2120C09-64CGT/F
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
78Q2120C09-64CGTR/F
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
78Q2120C09-CGTR/F
Manufacturer:
Maxim Integrated
Quantity:
10 000
10/100BASE-TX
Ethernet Transceiver
MR17 - INTERRUPT CONTROL/STATUS REGISTER
The Interrupt Control/Status Register provides the means for controlling and observing the events which trigger
an interrupt on the INTR pin. This register can also be used in a polling mode via the MII serial interface as a
means to observe key events within the PHY via one register address. These bits are cleared after the register is
read. Bits 8-15 of this register, when set to logic one, enable their corresponding bit in the lower byte to signal an
interrupt on the INTR pin. The level of this interrupt can be set via MR16.14.
BIT
17.15
17.14
17.13
17.12
17.11
17.10
17.9
17.8
17.7
17.6
17.5
17.4
17.3
17.2
17.1
17.0
SYMBOL
JABBER IE
RXER IE
PRX IE
PFD IE
LP-AC K IE
LS-CHG IE
RFAULT IE
ANEG-COMP IE
JABBER INT
RXER INT
PRX INT
PDF INT
LP-ACK INT
LS-CHG INT
RFAULT INT
ANEG-COMP INT
R, W, 0
R, W, 0
R, W, 0
R, W, 0
R, W, 0
R, W, 0
R, W, 0
R, W, 0
TYPE
RC, 0
RC, 0
RC, 0
RC, 0
RC, 0
RC, 0
RC, 0
RC, 0
DESCRIPTION
JABBER INTERRUPT ENABLE BIT
RECEIVE ERROR INTERRUPT ENABLE BIT
PAGE RECEIVED INTERRUPT ENABLE BIT
PARALLEL DETECT FAULT INTERRUPT ENABLE BIT
LINK PARTNER ACKNOWLEDGE INTERRUPT ENABLE BIT
LINK STATUS CHANGE INTERRUPT ENABLE BIT
REMOTE FAULT INTERRUPT ENABLE BIT
AUTO-NEGOTIATION COMPLETE INTERRUPT ENABLE BIT
JABBER INTERRUPT: This bit is set when a jabber event is indicated
by the 10BASE-T circuitry.
RECEIVE ERROR INTERRUPT: This bit is set when the RX_ER
signal transitions high.
PAGE RECEIVE INTERRUPT: This bit is set when a new page has
been received from the link partner during auto-negotiation.
PARALLEL DETECT FAULT INTERRUPT: This bit is set by the auto-
negotiation logic when a parallel detect fault condition is indicated.
LINK PARTNER ACKNOWLEDGE INTERRUPT: This bit is set by the
auto-negotiation logic when FLP bursts are received with the
acknowledge bit set.
LINK STATUS CHANGE INTERRUPT: This bit is set when the link
transitions from an OK status to a fail status or vice versa.
REMOTE FAULT INTERRUPT: This bit is set when a remote fault
condition has been indicated by the link partner.
AUTO-NEGOTIATION COMPLETE INTERRUPT: This bit is set by the
auto-negotiation logic upon successful completion of auto-negotiation.
17

Related parts for 78Q2120