78Q2120 Teridian Semiconductor Corp. (TDK Semiconductor), 78Q2120 Datasheet - Page 13

• Manufacturer Part Number: 78Q2120
• Description: 10/100 Ethernet PHYS
• Manufacturer: Teridian Semiconductor Corp. (TDK Semiconductor)

10/100BASE-TX
Ethernet Transceiver
MR1 - STATUS REGISTER
Bits 1.15 through 1.11 reflect the ability of the 78Q2120-64CGT as configured by the TECH[2:0] pins They do not
reflect any ability changes made via the MII management interface to bits 0.13 (SPEEDSL), 0.12 (ANEGEN) and 0.8
(DUPLEX).
MR2, 3 - PHY IDENTIFIER REGISTER
3.15:10
2.15:0
1.10:6
3.9:4
3.3:0
1.15
1.14
1.13
1.12
1.11
BIT
1.5
1.4
1.3
1.2
1.1
1.0
SYMBOL
RFAULT
100X_H
ANEGC
100X_F
ANEGA
10T_H
10T_F
100T4
RSVD
EXTD
LINK
OUI
OUI
JAB
MN
RN
R, 111001
R, 010100
R, 0300h
R, 0, RC
R, 0, RC
TYPE
R, (1)
R, (1)
R, (1)
R, (1)
R, (1)
R, 0
R, 0
R, 0
R, 0
R, 1
R
ORGANIZATIONALLY UNIQUE IDENTIFIER: This value is 00-
C0-39 for TDK Semiconductor Corporation. This translates to a
value of 300h for this register.
ORGANIZATIONALLY UNIQUE IDENTIFIER: Remaining 6 bits
of the OUI.
MODEL NUMBER: The last 2 digits of the model number
78Q2120-64CGT is encoded into the 6 bits. (20d = 14h)
REVISION NUMBER: For example, a value of 0010 corresponds
to the second version of the silicon.
DESCRIPTION
100BASE-T4 ABILITY: This bit is permanently held at logic zero to
indicate that the 78Q2120-64CGT is not capable of 100BASE-T4.
100BASE-TX FULL DUPLEX ABILITY: (0 = not able, 1 = able)
100BASE-TX HALF DUPLEX ABILITY: (0 = not able, 1 = able)
10BASE-T FULL DUPLEX ABILITY: (0 = not able, 1 = able)
10BASE-T HALF DUPLEX ABILITY: (0 = not able, 1 = able)
RESERVED
AUTO-NEGOTIATION COMPLETE: A logic one indicates a) that
the auto-negotiation process has completed, b) that the contents of
registers MR4, 5, and 6 are valid, and c) that a highest common
denominator rate and mode have been found.
REMOTE FAULT: A logic one indicates that a remote fault condition
has been detected. It remains set until it is cleared. This bit can only
be cleared by reading this register (MR1) via the management
interface.
AUTO-NEGOTIATION ABILITY: This bit, when set, indicates the
ability to perform auto-negotiation. The value of this bit is
determined by the ANEGA pin.
LINK STATUS: A logic one indicates that a valid link has been
established. If the link status should transition from an OK status to
a NOT-OK status, this bit will become cleared and remain cleared
until it is read.
JABBER DETECT: In 10Base-T mode, this bit is set during a jabber
event. After a jabber event it remains set until cleared by a read
operation.
EXTENDED CAPABILITY: This bit is permanently set to logic one
to indicate that the 78Q2120-64CGT provides an extended register
set (MR2 and beyond).
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