78Q2120 Teridian Semiconductor Corp. (TDK Semiconductor), 78Q2120 Datasheet - Page 11

• Manufacturer Part Number: 78Q2120
• Description: 10/100 Ethernet PHYS
• Manufacturer: Teridian Semiconductor Corp. (TDK Semiconductor)

10/100BASE-TX
Ethernet Transceiver
MR0 - CONTROL REGISTER
0.15
0.14
0.13
0.12
0.11
0.10
BIT
0.9
SPEEDSL
SYMBOL
ANEGEN
LOOPBK
PWRDN
RANEG
RESET
ISO
R, W, 0, SC
R, W, 0, SC
R, W, (1)
R, W, (1)
R, W, (0)
R, W, 0
R, W, 0
TYPE
DESCRIPTION
RESET: Setting this bit to logic one resets the entire 78Q2120-
64CGT. This bit is self clearing.
LOOPBACK: When this bit is set, no transmission of data on the
network medium occurs and any receive data on the network
medium is ignored. By default, the loopback signal path will
encompass as much of the 78Q2120-64CGT circuitry as possible.
SPEED SELECTION: This bit determines the speed of operation of
the 78Q2120-64CGT. A logic one indicates 100BASE-TX operation
and a logic zero indicates 10BASE-T. When auto-negotiation is
enabled, this bit will have no effect on the 78Q2120-64CGT. At
reset, this bit reflects the highest operating speed allowed by the
TECH [2:0] pins. The MII can write to this bit, but the bit will change
value only if the new value is allowed by the TECH [2:0] pins.
AUTO-NEGOTIATION ENABLE: The auto-negotiation process is
enabled by setting this bit to a logic one. This bit can only be set to
logic one if the ANEGA pin is a logic one and will default to a logic
one upon reset in this case. If this bit is cleared to logic zero,
manual speed and duplex mode selection is accomplished through
bits 0.8 (DUPLEX) and 0.13 (SPEEDSL) of the configuration
register or the TECH[2:0] pins according to the table shown in the
section describing the TECH[2:0] pins. If the ANEGA pin is brought
from zero to one and reset is not asserted, this bit will remain at
zero until a one is written.
POWER-DOWN: The 78Q2120-64CGT may be placed in a low
power consumption state by setting this bit to logic one. While in
power-down
management transactions. The power-down state can also be
achieved by setting PWRDN pin high.
ISOLATE: When set, the 78Q2120-64CGT will present a high
impedance on its MII output pins. This allows for multiple PHY to be
attached to the same MII interface. When the 78Q2120-64CGT is
isolated, it stills responds to management transactions. The default
value of this bit depends on the ISODEF pin. When ISODEF pin is
tied high the ISO bit defaults to high. When ISODEF pin is tied low,
the ISO bit defaults to low. The same high impedance state can be
achieved through the ISO pin.
RESTART AUTO-NEGOTIATION: Normally, the auto-negotiation
process is started at power-up. The process can be restarted by
setting this bit to logic one. This bit is self clearing.
11
state,
the
78Q2120-64CGT
still
responds
to