78Q2120 Teridian Semiconductor Corp. (TDK Semiconductor), 78Q2120 Datasheet - Page 15

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78Q2120

Manufacturer Part Number
78Q2120
Description
10/100 Ethernet PHYS
Manufacturer
Teridian Semiconductor Corp. (TDK Semiconductor)
Datasheet

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10/100BASE-TX
Ethernet Transceiver
MR6 - AUTO-NEGOTIATION EXPANSION REGISTER
MR16 - VENDOR SPECIFIC REGISTER
16.15
16.14
16.13
16.12
16.11
16.10
6.15:5
16.9
16.8
BIT
6.4
6.3
6.2
6.1
6.0
LOOPBACK
INT LEVEL
SQE TEST
NATURAL
LPANEGA
SYMBOL
INHIBIT
TXHIM
RSVD
RSVD
RSVD
LPNPA
RPTR
10BT
RSVD
NPA
PRX
PDF
R, W, (0)
R, 0, RC
R, 0, RC
R, W, 0
R, W, 0
R, W, 0
R, W, 0
TYPE
R, 0
R, 0
R, 0
R, 0
R, 0
R, 0
R, 1
DESCRIPTION
RESERVED
PARALLEL DETECTION FAULT: When set, it indicates that more
than one technology was detected during link up. This bit is cleared
when read.
LINK PARTNER NEXT PAGE ABLE: When set, it indicates that the
link partner supports the next page function.
NEXT PAGE ABLE: Permanently tied to logic zero since the
78Q2120-64CGT does not support next page function.
PAGE RECEIVED: Set when a properly matched link code word has
been received into the Auto-negotiation Link Partner. This bit is
cleared when read.
LINK PARTNER AUTO-NEGOTIATION ABLE: When set it indicates
that the link partner is able to participate in the auto-negotiation
function.
REPEATER MODE: When set, this bit puts the chip into repeater
mode. In this mode, full duplex is prohibited, CRS responds to
receive activity only and, in 10BASE-T mode, the SQE test function
is disabled.
When this bit is a zero, the INTR pin is forced low to signal an
interrupt. Setting this bit causes the INTR pin to be forced high to
signal an interrupt.
RESERVED
TRANSMIT HIGH IMPEDANCE: When this bit is set, the transmitter
UTP drivers are in a high impedance state and TXCLK is tri-stated.
The receive circuitry remains fully functional. Only a reset condition
will automatically clear this bit.
Setting this bit disables 10BASE-T SQE testing. By default, when
this bit is a zero, the SQE test is performed by generating a COL
pulse following the completion of a packet transmission.
Setting this bit causes transmitted data on TXD to be automatically
looped back to the RXD receive signals when 10BASE-T mode is
enabled.
RESERVED
RESERVED
15

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