78Q2120 Teridian Semiconductor Corp. (TDK Semiconductor), 78Q2120 Datasheet - Page 3

• Manufacturer Part Number: 78Q2120
• Description: 10/100 Ethernet PHYS
• Manufacturer: Teridian Semiconductor Corp. (TDK Semiconductor)

10/100BASE-TX
Ethernet Transceiver
receive
preambles are detected, the PLL adjusts its phase
and re-synchronizes with the incoming Manchester
data.
100BASE-TX OPERATION
100BASE-TX Transmit
The 78Q2120-64CGT contains all of the necessary
circuitry to convert the transmit MII signaling from a
MAC to an IEEE-802.3 compliant data-stream
driving Cat-5 UTP cabling.
interface maps 4 bit nibbles from the MII to 5 bit
code groups as defined in table 24-1 of IEEE-802.3.
These 5 bit code groups are then scrambled and
converted to a serial stream before being sent to the
MLT-3 pulse shaping circuitry and line driver. The
pulse-shaper uses current modulation to produce the
desired output waveform. Controlled rise/fall time in
MLT-3 signal is achieved using an accurately
controlled C/I filter.
external 1:1 isolation transformer to interface with
the line media. The center-tap of the primary side of
the transformer should be connected to Vcc.
100BASE-TX Receive
The 78Q2120-64CGT receives a 125MBaud MLT-3
signal through a 1:1 transformer. The signal then
goes through a combination of adaptive offset
adjustment
adaptive equalization. The effect of these circuits is
to sense the amount of dispersion and attenuation
caused by the cable and transformer, and restore
the received pulses to logic levels. The amount of
gain and equalization applied to the pulses varies
with the detected attenuation and dispersion and,
therefore, with the length of the cable.
78Q2120-64CGT can recover up to a 10dB of loss in
signal amplitude at 16 MHz.
represented as test-chan 5 in Annex A of the ANSI
X3.263:199X specification and corresponds to
approximately 140m of Cat5 UTP cabling.
equalized MLT-3 data signal is sliced and the
resulting bit-stream is presented to the clock
recovery PLL and to a serial to parallel converter.
The parallel data from the converter is then
descrambled and aligned into 5 bit code groups.
The receive PCS interface maps these code groups
to 4 bit data for the MII as outlined in table 24-1 in
Clause 24 of IEEE-802.3.
PCS Bypass mode
The PCS Bypass mode is entered by pulling PCSBP
periods.
(baseline
The line driver requires an
When
wander
The internal PCS
Manchester-coded
correction)
This loss is
The
The
and
3
high or by setting register bit MR 16.1. In this mode
the 78Q2120-64CGT accepts scrambled 5 bit code
into the pins TX_ER and TXD[3:0]. TX_ER is the
MSB data input.
converted to an MLT-3 signal.
The received MLT-3 signal is converted to 5 bit NRZ
code groups and output from the RX_ER and
RXD[3:0] pins. The RX_ER pin is the MSB data
output. The RX_DV and TX_EN pins are unused in
PCS Bypass mode.
10BASE-T OPERATION
10BASE-T Transmit
The 78Q2120-64CGT takes 4 bit parallel NRZ data
via the MII interface and passes it through a parallel
to serial converter. The data is then passed through
a Manchester encoder and then on to the twisted
pair pulse shaping circuitry and the twisted pair drive
circuitry. An advanced pulse shaper employs a Gm-
C filter to pre-distort the output waveform to meet the
output voltage template and spectral content
requirements detailed in Clause 14 of IEEE-802.3.
Interface to the twisted pair media is through two
external 50 ohm resistors and a center-tapped 1:1
transformer; no external filtering is required. During
auto-negotiation and during 10BASE-T idle periods,
link pulses are transmitted.
The 78Q2120-64CGT employs an onboard timer to
prevent the MAC from capturing a network through
excessively long transmissions. When this timer is
exceeded the chip enters the jabber state, and
transmission is disabled. The jabber state is exited
after the MII goes idle for 500ms ± 250ms.
10BASE-T Receive
The 78Q2120-64CGT receives Manchester encoded
10BASE-T data through the twisted pair inputs and
re-establishes logic levels through a slicer with a
smart squelch function.
adjusts its level after valid data with the appropriate
levels are detected.
10BASE-T PLL where the clock is recovered, data is
re-timed and passed through a Manchester decoder.
From here data enters the serial to parallel converter
for transmission to the MAC via the media
independent interface. Interface to the twisted pair
media is through an external 100 ohm resistor and a
1:1 center-tapped transformer; no external filtering is
required.
corrected in the internal circuitry.
Polarity information is detected and
The 5 bit code groups are
Data is passed on to the
The slicer automatically