78Q2120 Teridian Semiconductor Corp. (TDK Semiconductor), 78Q2120 Datasheet - Page 18

• Manufacturer Part Number: 78Q2120
• Description: 10/100 Ethernet PHYS
• Manufacturer: Teridian Semiconductor Corp. (TDK Semiconductor)

MR18 - DIAGNOSTIC REGISTER
BIT
18.15:13
18.12
18.11
18.10
18.9
18.8
18.7:0
RX-PASS
RX-LOCK
SYMBOL
ANEGF
RSVD
RSVD
RATE
DPLX
R, W, 0
R,0,RC
TYPE
R, 0
R, 0
R, 0
R, 0
R, 0
DESCRIPTION
RESERVED
AUTO-NEGOTIATION FAIL: This bit is set when auto-negotiation
completes and no common technology was found. It remains set until
read.
DUPLEX: This bit indicates the result of the auto-negotiation for duplex
arbitration. If set it indicates that full-duplex was the highest common
denominator. If clear it indicates that half-duplex was the highest
common denominator.
RATE: This bit indicates the result of the auto-negotiation for data rate
arbitration. If set it indicates that 100BASE-TX was the highest common
denominator. If clear it indicates that 10BASE-T was the highest
common denominator.
RECEIVE PASS: In 10BASE-T mode, this bit indicates that Manchester
data has been detected. In 100BASE-TX mode, it indicates that a valid
received
locked on to).
RECEIVE LOCK: Indicates that the receive PLL has locked onto the
received signal for the selected speed of operation (10BASE-T or
100BASE-TX). This bit is cleared whenever a cycle-slip occurs, and
will remain cleared until it is read.
RESERVED. Must be zero.
signal
18
has
been
detected
Ethernet Transceiver
10/100BASE-TX
(but
not
necessarily