ATA5771 ATMEL Corporation, ATA5771 Datasheet - Page 114

• Manufacturer Part Number: ATA5771
• Manufacturer: ATMEL Corporation

62
ATtiny24/44/84
• Port A, Bit 6 – ADC6/DI/SDA/MOSI/OC1A/PCINT6
• Port A, Bit 7 – ADC7/OC0B/ICP1/PCINT7
Table 10-4 on page 62
overriding signals shown in
Table 10-4.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
• ADC6: Analog to Digital Converter, Channel 6
• SDA: Two-wire mode Serial Interface Data.
• DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port
• MOSI: Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a
• OC1A, Output Compare Match output: The PA6 pin can serve as an external output for the
• PCINT6: Pin Change Interrupt source 6. The PA6 pin can serve as an external interrupt
• ADC7: Analog to Digital Converter, Channel 7
• OC1B, Output Compare Match output: The PA7 pin can serve as an external output for the
• ICP1, Input Capture Pin: The PA7 pin can act as an Input Capture Pin for Timer/Counter1.
• PCINT7: Pin Change Interrupt source 7. The PA7 pin can serve as an external interrupt
functions, so pin must be configure as an input for DI function.
Slave, this pin is configured as an input regardless of the setting of DDA6. When the SPI is
enabled as a Master, the data direction of this pin is controlled by DDA6. When the pin is
forced by the SPI to be an input, the pull-up can still be controlled by the PORTA6 bit.
Timer/Counter1 Compare Match A. The pin has to be configured as an output (DDA6 set
(one)) to serve this function. This is also the output pin for the PWM mode timer function.
source for pin change interrupt 0.
Timer/Counter1 Compare Match B. The pin has to be configured as an output (DDA7 set
(one)) to serve this function. This is also the output pin for the PWM mode timer function.
source for pin change interrupt 0.
PA7/ADC7/OC0B/ICP1/
PCINT7
0
0
0
0
OC0B enable
OC0B
0
PCINT7 • PCIE0 + ADC7D
PCINT7/ICP1 Input
ADC7 Input
PCINT7 • PCIE0
Overriding Signals for Alternate Functions in PA7..PA5
and
Figure 10-5 on page
Table 10-6 on page 63
PA6/ADC6/DI/SDA/MOSI/
OC1A/ PCINT6
0
0
USIWM1
(SDA + PORTA6) • DDA6
(USIWM1 • DDA6) + OC1A
enable
( USIWM1• DDA6) • OC1A
0
USISIE + (PCINT6 • PCIE0)
+ ADC6D
USISIE + PCINT7 • PCIE0
DI/SDA/PCINT6 Input
ADC6 Input
58.
.
.
relate the alternate functions of Port A to the
PA5/ADC5/MISO/DO/
OC1B/ PCINT5
0
0
0
0
(USIWM1 • USIWM0) +
OC1B enable
USIWM1 • USIWM0 • DO +
(USIWM1 + USIWM0) •
OC1B
0
PCINT5 • PCIE + ADC5D
PCINT5 • PCIE
PCINT5 Input
ADC5 Input
8006G–AVR–01/08