ATA5771 ATMEL Corporation, ATA5771 Datasheet - Page 216

• Manufacturer Part Number: ATA5771
• Manufacturer: ATMEL Corporation

19.5.1
164
ATtiny24/44/84
Serial Programming Algorithm
When writing serial data to the ATtiny24/44/84, data is clocked on the rising edge of SCK.
When reading data from the ATtiny24/44/84, data is clocked on the falling edge of SCK. See
Figure 20-4
To program and verify the ATtiny24/44/84 in the Serial Programming mode, the following
sequence is recommended (see four byte instruction formats in
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of syn-
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
6. Any memory location can be verified by using the Read instruction which returns the
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed):
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
a time by supplying the 5 LSB of the address and data together with the Load Program
memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program memory
Page is stored by loading the Write Program memory Page instruction with the 3 MSB
of the address. If polling (RDY/BSY) is not used, the user must wait at least t
before issuing the next page. (See
gramming interface before the Flash write operation completes can result in incorrect
programming.
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling (RDY/BSY) is not used,
the user must wait at least t
page
grammed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one byte at a time by supplying the 2 LSB of the address and data together with the
Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by
loading the Write EEPROM Memory Page Instruction with the 4 MSB of the address.
When using EEPROM page access only byte locations loaded with the Load EEPROM
Memory Page instruction is altered. The remaining locations remain unchanged. If poll-
ing (RDY/BSY) is not used, the used must wait at least t
next page (See
file(s) need to be programmed.
content at the selected address at serial output MISO.
operation.
Set RESET to “1”.
Turn V
165.) In a chip erased device, no 0xFFs in the data file(s) need to be pro-
and
CC
power off.
Figure 20-5
Table 19-11 on page
for timing details.
CC
and GND while RESET and SCK are set to “0”. In some sys-
WD_EEPROM
Table 19-11 on page
165). In a chip erased device, no 0xFF in the data
before issuing the next byte. (See
WD_EEPROM
165.) Accessing the serial pro-
Table
19-12):
before issuing the
Table 19-11 on
WD_FLASH
8006G–AVR–01/08